A Step Towards Optimisation of 2 to 4 Decoder Using Farooq-Nikesh-Zaid Gate with Coplanar Crossing in Quantum Dot Cellular Automata

2020 ◽  
Vol 17 (5) ◽  
pp. 2120-2124
Author(s):  
R. Jayalakshmi ◽  
M. Senthil Kumaran ◽  
R. Amutha
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Complementary Metal Oxide Semiconductor ◽  
Basic Structure ◽  
Oxide Semiconductor ◽  
Nand Gate ◽  
Quantum Dot Cellular Automata ◽  
Wire Crossing ◽  
Majority Voter ◽  
Low Power Dissipation

The limitations of the existing Complementary Metal Oxide Semiconductor are leading the momentum to various new approaches like Quantum-dot Cellular Automata (QCA). QCA offers low power dissipation, less area and high switching speeds. The Majority Voter is the basic structure that votes out on the majority of the inputs to implement a Boolean Function. The QCA architectures are created by using majority gates with inverters or by using universal gates like AND–OR-Inverter and NAND–NOR-Inverter gate. This paper proposes a quantum-dot cellular automata 2 to 4 decoder using Universal Farooq-Nikesh-Zaid gate, which utilizes the NAND gate logic to implement the functionality. The design offers 33% reduction in the cell count, reduction in the area with Six Clock Phases in simple co planar wire crossing. The proposed design is validated using the QCA Designer tool.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

scholarly journals An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2707-2716
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Cell Count ◽  
Sequential Circuits ◽  
Design Tool ◽  
Oxide Semiconductor ◽  
Flip Flop ◽  
Xor Gate ◽  
Quantum Dot Cellular Automata ◽  
Layout Area

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

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