Numerical Design of Carrier Transporting Layer in Top-Gate InGaZnO Thin-Film Transistors for Controlling Potential Energy

2021 ◽  
Vol 21 (7) ◽  
pp. 3847-3852
Author(s):  
Do-Kyung Kim ◽  
Jihwan Park ◽  
Premkumar Vincent ◽  
Jun-Ik Park ◽  
Jaewon Jang ◽  
...  

Top-gate amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are designed with numerical analysis to control their electron potential energy. Design simulations show the effects of structural design on the electrical characteristics of these TFTs. In particular, the thicknesses of the channel (tch) and conducting (tc) layers, which play vital roles in TFT electrical performance, are varied from 1 to 50 nm to investigate the effect of thicknesses on the electron potential energies of the channel region and the electrode-semiconductor interfaces. The potential energies are precisely optimized for efficient charge transport, injection, and extraction, thus enhancing the electrical performance of these devices. It is also demonstrated that tch mainly affects mobility and threshold voltage, while tc mainly affects on-current. An acceptable threshold voltage of 0.55 V and high mobility of 14.7 cm2V−1s−1 are obtained with a tch of 30 nm and tc of 10 nm. Controllability of the electron potential energies and electrical performance of IGZO TFTs by means of structural design will contribute to realization of next-generation displays that have large areas and high resolutions.

Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 852 ◽  
Author(s):  
Seungbeom Choi ◽  
Kyung-Tae Kim ◽  
Sung Park ◽  
Yong-Hoon Kim

In this paper, we demonstrate high-mobility inkjet-printed indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) using a solution-processed Sr-doped Al2O3 (SAO) gate dielectric. Particularly, to enhance to the electrical properties of inkjet-printed IGZO TFTs, a linear-type printing pattern was adopted for printing the IGZO channel layer. Compared to dot array printing patterns (4 × 4 and 5 × 5 dot arrays), the linear-type pattern resulted in the formation of a relatively thin and uniform IGZO channel layer. Also, to improve the subthreshold characteristics and low-voltage operation of the device, a high-k and thin (~10 nm) SAO film was used as the gate dielectric layer. Compared to the devices with SiO2 gate dielectric, the inkjet-printed IGZO TFTs with SAO gate dielectric exhibited substantially high field-effect mobility (30.7 cm2/Vs). Moreover, the subthreshold slope and total trap density of states were also significantly reduced to 0.14 V/decade and 8.4 × 1011/cm2·eV, respectively.


2019 ◽  
Vol 9 (1) ◽  
Author(s):  
Zhuofa Chen ◽  
Dedong Han ◽  
Xing Zhang ◽  
Yi Wang

AbstractIn this paper, we investigated the performance of thin-film transistors (TFTs) with different channel configurations including single-active-layer (SAL) Sn-Zn-O (TZO), dual-active-layers (DAL) In-Sn-O (ITO)/TZO, and triple-active-layers (TAL) TZO/ITO/TZO. The TAL TFTs were found to combine the advantages of SAL TFTs (a low off-state current) and DAL TFTs (a high mobility and a low threshold voltage). The proposed TAL TFTs exhibit superior electrical performance, e.g. a high on-off state current ratio of 2 × 108, a low threshold voltage of 0.63 V, a high field effect mobility of 128.6 cm2/Vs, and a low off-state current of 3.3 pA. The surface morphology and characteristics of the ITO and TZO films were investigated and the TZO film was found to be C-axis-aligned crystalline (CAAC). A simplified resistance model was deduced to explain the channel resistance of the proposed TFTs. At last, TAL TFTs with different channel lengths were also discussed to show the stability and the uniformity of our fabrication process. Owing to its low-processing temperature, superior electrical performance, and low cost, TFTs with the proposed TAL channel configuration are highly promising for flexible displays where the polymeric substrates are heat-sensitive and a low processing temperature is desirable.


Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1875
Author(s):  
Hwan-Seok Jeong ◽  
Hyun Seok Cha ◽  
Seong Hyun Hwang ◽  
Hyuck-In Kwon

In this study, we examined the effects of the annealing atmosphere on the electrical performance and stability of high-mobility indium-gallium-tin oxide (IGTO) thin-film transistors (TFTs). The annealing process was performed at a temperature of 180 °C under N2, O2, or air atmosphere after the deposition of IGTO thin films by direct current magnetron sputtering. The field-effect mobility (μFE) of the N2- and O2-annealed IGTO TFTs was 26.6 cm2/V·s and 25.0 cm2/V·s, respectively; these values were higher than that of the air-annealed IGTO TFT (μFE = 23.5 cm2/V·s). Furthermore, the stability of the N2- and O2-annealed IGTO TFTs under the application of a positive bias stress (PBS) was greater than that of the air-annealed device. However, the N2-annealed IGTO TFT exhibited a larger threshold voltage shift under negative bias illumination stress (NBIS) compared with the O2- and air-annealed IGTO TFTs. The obtained results indicate that O2 gas is the most suitable environment for the heat treatment of IGTO TFTs to maximize their electrical properties and stability. The low electrical stability of the air-annealed IGTO TFT under PBS and the N2-annealed IGTO TFT under NBIS are primarily attributed to the high density of hydroxyl groups and oxygen vacancies in the channel layers, respectively.


2010 ◽  
Vol 1245 ◽  
Author(s):  
Anil Indluru ◽  
Sameer M Venugopal ◽  
David R Allee ◽  
Terry L Alford

AbstractHydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in many areas and the most important application is in active matrix liquid crystal display. However, the instability of the a-Si:H TFTs constrains their usability. These TFTs have been annealed at higher temperatures in hope of improving their electrical performance. But, higher anneal temperatures become a constraint when the TFTs are grown on polymer-based flexible substrates. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on PEN. Thin-film transistors are annealed at different anneal times (4 h, 24 h, and 48 h) and were stressed under different bias conditions. Sub-threshold slope and the off-current improved with anneal time. Off-current was reduced by two orders of magnitude for 48 hours annealed TFT and sub-threshold slope became steeper with longer annealing. At positive gate-bias-stress (20 V), threshold voltage shift (∆Vt) values are positive and exhibit a power-law time dependence. High temperature measurements indicate that longer annealed TFTs show improved performance and stability compared to unannealed TFTs. This improvement is due to reduction of interface trap density and good a-Si:H/insulator interface quality with anneal time.


2021 ◽  
Vol 6 (2) ◽  
pp. 21
Author(s):  
Poreddy Manojreddy ◽  
Srikanth Itapu ◽  
Jammalamadaka Krishna Ravali ◽  
Selvendran Sakkarai

We utilized laser irradiation as a potential technique in tuning the electrical performance of NiOx/SiO2 thin film transistors (TFTs). By optimizing the laser fluence and the number of laser pulses, the TFT performance was evaluated in terms of mobility, threshold voltage, on/off current ratio and subthreshold swing, all of which were derived from the transfer and output characteristics. The 500 laser pulses-irradiated NiOx/SiO2 TFT exhibited an enhanced mobility of 3 cm2/V-s from a value of 1.25 cm2/V-s for as-deposited NiOx/SiO2 TFT, subthreshold swing of 0.65 V/decade, on/off current ratio of 6.5 × 104 and threshold voltage of −12.2 V. The concentration of defect gap states as a result of light absorption processes explains the enhanced performance of laser-irradiated NiOx. Additionally, laser irradiation results in complex thermal and photo thermal changes, thus resulting in an enhanced electrical performance of the p-type NiOx/SiO2 TFT structure.


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