Design of a Low Voltage High Symmetrical Slew Rate Opamp Based on Self Cascode in UMC 0.18 μm

2015 ◽  
Vol 11 (4) ◽  
pp. 498-503
Author(s):  
Carmelo Zuccarotto ◽  
Anna Richelli ◽  
Zsolt Kovàcs-Vajna
Keyword(s):  
Low Voltage ◽  
Slew Rate ◽  
Self Cascode

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Reconfigurable low voltage low power dual-band self-cascode current-reuse quasi-differential LNA for 5G

2019 ◽  
Vol 92 ◽  
pp. 104602 ◽  
Author(s):  
K. Hari Kishore ◽  
V. Senthil Rajan ◽  
R. Sanjay ◽  
B. Venkataramani
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Dual Band ◽  
Current Reuse ◽  
Self Cascode

A high slew rate, low voltage CMOS class-AB amplifier

2014 ◽  
Author(s):  
Kunchala Sivakumari ◽  
Avireni Srinivasulu ◽  
V. Venkata Reddy
Keyword(s):  
Low Voltage ◽  
Slew Rate ◽  
Class Ab

Self Cascode: A Promising Low Voltage Analog Design Technique

2009 ◽  
Vol 50 (2) ◽  
pp. 73-83 ◽  
Author(s):  
Jasdeep Kaur ◽  
Nupur Prakash ◽  
S.S. Rajput
Keyword(s):  
Low Voltage ◽  
Analog Design ◽  
Design Technique ◽  
Self Cascode
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