Hardware Description in Verilog

Author(s):  
Zainalabedin Navabi
Keyword(s):  
Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.


2011 ◽  
Vol 187 ◽  
pp. 741-745 ◽  
Author(s):  
Juan Hua Zhu ◽  
Ang Wu ◽  
Juan Fang Zhu

A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.


2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.


2012 ◽  
Vol 58 (4) ◽  
pp. 397-402 ◽  
Author(s):  
Michał Doligalski ◽  
Marian Adamski

Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL language


2005 ◽  
Vol 295-296 ◽  
pp. 589-594
Author(s):  
J.P. Wang ◽  
W. Zhou ◽  
W.F. Tian ◽  
Z.H. Jin

This paper describes the design of an intelligent multi-gyro measurement device to measure and monitor an inertial unit composed of three dynamically tuned gyros (DTGs). A 16-bit microprogrammed control unit is programmed to fulfill the functions of signal processing, logic control and serial communication with a master computer. An FPGA, designed by using Verilog Hardware Description Language, is used to realize high speed 16-bit reversible counters for output pulses of the DTG digital dynamic balance circuits. The count values represent the angular motion of the inertial unit. A stepping electric bridge is employed to measure the resistance of thermal resistors within the gyros in a wide temperature environment. The resistance represents the working temperature of the gyros. An effective calibration method for the bridge is developed to eliminate the resistance measurement error. A test system is established to examine whether the device meets the user requirements. Results of the tests show that the device has a good performance. A trial use has proved that the device is stable and reliable and that it satisfies the demand of the user.


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