MOSFET-Based Low-Power Hardware Design for Autonomous Applications

In the OTN+WiMax control system of Metro, the use of wireless backhaul can reduce costs and increase security. This paper presented a variety of OTN+WiMax hardware solution for Metro monitoring systems for wireless backhaul system by comparing the variety of chips; For WiMAX, Wi-Fi coexisting wireless backhaul situation, we put forward the hardware design using low-power high-speed chip of Infineon's SMARTi hardware design,, and pointed out that the design programme belongs to energy-saving green environmental. Also we used Intel WiMAX Connection 2,400 chip design hardware programme of wireless backhaul system for monitoring. At last, The software radio technology is applied to wireless backhaul system.

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Hardware Design of Low-Power ZigBee Wireless Sensor Network Node

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.926-930.2482 ◽

2014 ◽

Vol 926-930 ◽

pp. 2482-2485

Author(s):

Si Zu Hou ◽

Ning Li

Keyword(s):

Wireless Sensor Network ◽

Low Power ◽

Sensor Network ◽

Low Cost ◽

Hardware Design ◽

Wireless Sensor ◽

Important Indicator ◽

Network Nodes ◽

Zigbee Technology ◽

The Cost

ZigBee technology is widely used in wireless sensor networks with the advantages of low power, low cost, convenient networking, etc. Design of ZigBee-based wireless sensor network nodes have become a demand. The nodes are generally placed in some occasions where the power supply inconvenient and require battery-powered, so the low-power of the nodes is an important indicator. The node chose CC2530 as the hardware core and transplanted Z-Stack protocol stack. It collected different data through different sensors and used ZigBee technology for wireless communication. This article describes the process of node hardware design, and reduces the power consumption of the node with choosing low-power devices, reducing the operating frequency and other methods. Low-power node saves the cost and increases the life of the nodes and the network. So it is good for increasing the continuity and stability of the network.

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Development of New Type Centralized Engineering Seismograph

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.333-335.2412 ◽

2013 ◽

Vol 333-335 ◽

pp. 2412-2416

Author(s):

Jin Feng Yan ◽

Ming Deng ◽

Yan Jun Li ◽

Qi Sheng Zhang

Keyword(s):

Power Consumption ◽

Embedded System ◽

Low Power ◽

Program Implementation ◽

High Performance ◽

Hardware Design ◽

Low Power Consumption ◽

System Solution ◽

Software Program ◽

New Type

SoPC technology is a high-performance, low-power consumption embedded system solution based on embedded microprocessor, providing a new way for developing new type centralized engineering seismograph. The paper presents the development of a new type centralized engineering seismograph based on SoPC technology, which adopts FPGA design based on SoPC technology for the hardware design and embedded software program development of the 48-channel engineering seismograph. According to actual needs of currently available centralized engineering seismograph, combining the actual characteristics of SoPC embedded technology, a portable, low-power consumption and high-performance new type centralized engineering seismograph is constructed. The paper describes the hardware design and software program implementation of the centralized engineering seismograph in detail.

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A LOW-POWER PARAMETERIZED HARDWARE DESIGN FOR THE ONE-DIMENSIONAL DISCRETE FOURIER TRANSFORM OF VARIABLE LENGTHS

Journal of Circuits System and Computers ◽

10.1142/s0218126602000549 ◽

2002 ◽

Vol 11 (04) ◽

pp. 405-426 ◽

Cited By ~ 1

Author(s):

JIUN-IN GUO ◽

CHIEN-CHANG LIN ◽

CHIH-DA CHIEN

Keyword(s):

Fourier Transform ◽

Low Power ◽

Discrete Fourier Transform ◽

Hardware Design ◽

Ip Core ◽

Distributed Arithmetic ◽

One Dimensional ◽

System Requirements ◽

Block Based ◽

The One

This paper presents a new low-power parameterized hardware design for the one-dimensional (1D) discrete Fourier transform (DFT) of variable lengths. By combining the cyclic convolution formulation, block-based distributed arithmetic (BDA), and Cooley–Tukey decomposition algorithm together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 256 to 4096 points and with different modes of performance. The proposed design can perform different lengths of DFT computation through the configuration of parameters, which not only provides the flexibility in computing different length DFT but also facilitates the performance-driven design considerations in terms of power consumption and processing speeds, that is, we can configure the proposed design in different modes of performance by setting different parameters. This feature is beneficial to developing a parameterized DFT soft Intellectual Property (IP) core or hard IP core for meeting the system requirements of different silicon-on-a-chip (SOC) applications as compared with the existing fixed length DFT designs.

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