Effects of Wafer Cleaning on the Interconnect Structure and Its Electrical Properties during the Al Dual Damascene Process for the Fabrication of Sub-100 nm Memory Devices

2005 ◽  
Vol 38 (11) ◽  
pp. 922-928 ◽  
Author(s):  
Hyun-Kyu Ryu ◽  
Yil-Wook Kim ◽  
Chee Burm Shin ◽  
Chang-Koo Kim
Keyword(s):  
Electrical Properties ◽  
Memory Devices ◽  
Dual Damascene ◽  
Damascene Process ◽  
Wafer Cleaning

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Inorganic Si-O-C Antireflection Coating at 193 nm for Cu Dual Damascene Process

2003 ◽  
Vol 150 (1) ◽  
pp. G58 ◽  
Author(s):  
Sang-Yun Lee ◽  
Yong-Bae Kim ◽  
Jeong Soo Byun
Keyword(s):  
Antireflection Coating ◽  
Dual Damascene ◽  
Damascene Process ◽  
193 Nm

Microstructural effect of gadolinium oxide nanocrystals upon annealing on electrical properties of memory devices

2012 ◽  
Vol 520 (17) ◽  
pp. 5579-5583 ◽  
Author(s):  
Michael R.S. Huang ◽  
Chuan-Pu Liu ◽  
Jer-Chyi Wang ◽  
Yu-Kai Chen ◽  
Chao-Sung Lai ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gadolinium Oxide ◽  
Memory Devices ◽  
Microstructural Effect

Iron- and iron oxide-filled multi-walled carbon nanotubes: Electrical properties and memory devices

2007 ◽  
Vol 444 (4-6) ◽  
pp. 304-308 ◽  
Author(s):  
Carlos E. Cava ◽  
Ricardo Possagno ◽  
Mariane C. Schnitzler ◽  
Paulo C. Roman ◽  
Marcela M. Oliveira ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
Iron Oxide ◽  
Electrical Properties ◽  
Memory Devices ◽  
Multi Walled Carbon Nanotubes ◽  
Walled Carbon Nanotubes

A nanoscale approach to the electrical properties of MOS memory devices with Si-nanocrystals

2005 ◽  
Vol 80 ◽  
pp. 268-271 ◽  
Author(s):  
M. Porti ◽  
M. Avidano ◽  
M. Nafrı́a ◽  
X. Aymerich ◽  
J. Carreras ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Memory Devices ◽  
Si Nanocrystals

Evaluation of PECVD a-SiC:H as a Cu Diffusion Barrier Layer of Cu Dual Damascene Process

2000 ◽  
Author(s):  
Soo Gun Lee ◽  
Hyeok-Sang Oh ◽  
Hong-Jae Shin ◽  
Jin-Gi Hong ◽  
Hyeon-Deok Lee ◽  
...  
Keyword(s):  
Barrier Layer ◽  
Diffusion Barrier ◽  
Dual Damascene ◽  
Damascene Process ◽  
Diffusion Barrier Layer ◽  
Cu Diffusion Barrier
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