A 5.7 mW, UWB LNA for Wireless Applications Using Noise Canceling Technique in 90 nm CMOS

Frequenz ◽  
2020 ◽  
Vol 74 (1-2) ◽  
pp. 83-93
Author(s):  
Vikram Singh ◽  
Sandeep Kumar Arya ◽  
Manoj Kumar
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Low Noise ◽  
Ultra Wideband ◽  
Common Source ◽  
Cmos Process ◽  
Second Stage ◽  
Input Matching ◽  
Noise Amplifier ◽  
Noise Canceling

AbstractA 3–12 GHz ultra-wideband (UWB) low noise amplifier (LNA) is proposed in this paper. The first stage common-gate (CG), common-source (CS) noise canceling approach is used to achieve low noise-figure (NF). CG configuration at the input stage provides wideband input-matching. The noise of CG transistor is cancelled by systematically added two parallel CS transistors, whose outputs are cascoded in second stage. In order to achieve flat power gain (S21) response, a series peaking inductor is used in the second stage. The proposed LNA is designed in 90 nm CMOS process with chip-layout area of 0.467 mm2 and in comparison to the existing LNAs, it consumes a low power of 5.7 mW from a 1 V supply. The achieved input-reflection coefficient (S11) is <−7.5 dB, output-reflection coefficient (S22) is <−7.6 dB with NF < 5.8 dB for 3–12 GHz UWB and third-order intercept point (IIP3) of −19 dBm. It achieves high and flat S21 of 20.84 ± 0.28 dB over 4.2–10 GHz, with NF ranging from 2.6–3.6 dB.

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

scholarly journals A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

2018 ◽  
Vol 8 (4) ◽  
pp. 42
Author(s):  
Vikram Singh ◽  
Sandeep Arya ◽  
Manoj Kumar
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Average Power ◽  
Low Noise ◽  
Ultra Wideband ◽  
Common Source ◽  
Power Gain ◽  
Wireless Applications ◽  
Common Gate ◽  
Noise Amplifier

An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S22). It achieves an average power gain (S21) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S11) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S22) of less than −10.6 dB with a very high reversion isolation (S12) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.

A 3–14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless Applications in 90 nm CMOS

2019 ◽  
Vol 28 (04) ◽  
pp. 1950056 ◽  
Author(s):  
Vikram Singh ◽  
Sandeep Kumar Arya ◽  
Manoj Kumar
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Impedance Matching ◽  
Low Noise ◽  
Ultra Wideband ◽  
Common Source ◽  
Cmos Process ◽  
Frequency Range ◽  
Continuous Growth ◽  
Common Gate

Inspired from continuous growth in the field of low power and low noise wireless communication devices, a low noise amplifier (LNA) using self-body biased common-gate (CG) configuration is presented in this paper. The proposed LNA is designed for 3–14[Formula: see text]GHz ultra-wideband (UWB) frequency range using 90[Formula: see text]nm CMOS process. Common-gate configuration with self-body biasing has been used at the input stage to provide wideband input matching with low noise figure (NF) for the complete UWB frequency. An impedance matching network consisting of parallel to series RLC network has been used between common-gate and cascaded common source (CS) stages. Two stages of the CS configuration have been used for bandwidth enhancement and to increase the power gain (S[Formula: see text]) with acceptable NF. Buffer stage at the output has been used to achieve output reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.8[Formula: see text]dB. The proposed LNA achieves an average S[Formula: see text] of 15.9[Formula: see text][Formula: see text][Formula: see text]0.7[Formula: see text]dB with a maximum of 16.7[Formula: see text]dB at 3.0[Formula: see text]GHz and NF of 1.68–2.7[Formula: see text]dB for 3.1–10.6[Formula: see text]GHz UWB frequency range. It provides input reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.2[Formula: see text]dB, reverse isolation (S[Formula: see text]) less than [Formula: see text]75.8[Formula: see text]dB and a NF of 1.68–4.0[Formula: see text]dB throughout the proposed UWB frequency range. The proposed LNA provides input 1[Formula: see text]dB compression point (P1dB) of [Formula: see text]13[Formula: see text]dBm and input third-order intercept point (IIP3) of [Formula: see text]8[Formula: see text]dBm at 6[Formula: see text]GHz. It consumes 20.1[Formula: see text]mW of power from a 1.2[Formula: see text]V power supply.

scholarly journals Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

2021 ◽  
pp. 85-94
Author(s):  
Dr. Rashmi S B ◽  
Mr. Raghavendra B ◽  
Mr. Sanketh V
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Common Source ◽  
Frequency Range ◽  
Common Gate ◽  
Noise Amplifier

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

A 1.4mW 900MHz LNA with Noise-Canceling Technique in 130nm CMOS Process

2017 ◽  
Vol 27 (01) ◽  
pp. 1850003 ◽  
Author(s):  
Shaomin Huang ◽  
Zhongpan Yang ◽  
Chao Hua
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Measurement Results ◽  
Common Gate ◽  
Noise Amplifier ◽  
Noise Canceling

A noise-canceling low noise amplifier (LNA) structure is proposed in this paper. The LNA works in the 900[Formula: see text]MHz ISM band. The techniques of noise canceling and current-reusing are proposed to improve the noise performance and reduce the power dissipation. The noise cancellation schema is realized by mutually canceling the noise currents of the common-source and common-gate amplifiers. A prototype of the LNA is designed and fabricated in a standard 130[Formula: see text]nm CMOS process. Measurement results under a 1.2[Formula: see text]V supply voltage show that the proposed LNA achieves a voltage gain of 18[Formula: see text]dB and a noise figure of 2[Formula: see text]dB. The whole circuit only consumes a power dissipation of 1.4[Formula: see text]mW.

A 3.1~10.6 Ghz Ultra-Wideband SiGe Low Noise Amplifier with Current-Reused Technique

2011 ◽  
Vol 130-134 ◽  
pp. 3251-3254
Author(s):  
Kang Li ◽  
Chi Liu ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chao Xian Zhu ◽  
...  
Keyword(s):  
Reflection Coefficient ◽  
Silicon Germanium ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Total Power ◽  
Input Matching ◽  
Total Power Consumption ◽  
Noise Amplifier

A 3.1 ~ 10.6 GHz Ultra-Wideband SiGe Low Noise Amplifier (LNA) is proposed. This low noise amplifier utilizes a current-reused technique to increase the gain and extend the bandwidth. We have a detailed analysis for the input matching, noise figure, gain and other features. The LNA was designed with the TSMC 0.35µm bipolar silicon-germanium (SiGe) processes. Simulation results show that the input reflection coefficient is less than-9dB, the output reflection coefficient is less than-10dB, the maximum power gain of 17 dB and the minimum noise factor (NF) of 2.35dB. The total power consumption is 6.2 mW with 2.5V power supply.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

2021 ◽  
pp. 11-20
Author(s):  
Nguyen Huu Tho
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Wide Band ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Wide Range ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

2011 ◽  
Vol 403-408 ◽  
pp. 2809-2813
Author(s):  
Kuan Bao ◽  
Xiang Ning Fan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Fully Integrated ◽  
Input Matching ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

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