scholarly journals De-multiplexing free on-chip low-loss multimode switch enabling reconfigurable inter-mode and inter-path routing

Nanophotonics ◽  
2018 ◽  
Vol 7 (9) ◽  
pp. 1571-1580 ◽  
Author(s):  
Chunlei Sun ◽  
Wenhao Wu ◽  
Yu Yu ◽  
Guanyu Chen ◽  
Xinliang Zhang ◽  
...  
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Optical Network ◽  
Low Loss ◽  
Switch Fabrics ◽  
Novel Structure ◽  
On Chip ◽  
High Level ◽  
Optical Paths ◽  
Insertion Losses

AbstractSwitching and routing are critical functionalities for a reconfigurable bandwidth-dense optical network, and great efforts had been made to accommodate mode-division multiplexing technology. Although the reconfigurable routing for spatial-mode groups between different optical paths was realized recently, a demultiplexing-switching-multiplexing process is necessary. Here we present a simplified and compact on-chip 2×2 multimode switch that can be easily upgradable to a larger scale. Fully and reconfigurable routing between not only optical paths but also spatial modes is achieved. To obtain a low loss multimode processing, a novel structure free from demultiplexing and re-multiplexing operations is adopted. The switch enables minimum and maximum insertion losses of 0.3 and 1.2 dB, with a compact footprint of 433 μm×433 μm and low crosstalk of <−16.6 dB for all channels. It is further extended to two types of 4×4 switch fabrics with cross-bar and ring-bus architectures, as demonstrations of high-level integration. System characterization with 32 Gb/s high-speed modulated signals is also carried out, reaching up to 256 Gb/s aggregate throughput. These results verify a general solution of 2×2 multimode switch for reconfigurable inter-mode and inter-path routing applicable in large-scale and high-density multimode optical network.

scholarly journals Dense-RefineDet for Traffic Sign Detection and Classification

Sensors ◽  
2020 ◽  
Vol 20 (22) ◽  
pp. 6570
Author(s):  
Chang Sun ◽  
Yibo Ai ◽  
Sheng Wang ◽  
Weidong Zhang
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Design Method ◽  
Contextual Information ◽  
Real Life ◽  
Single Shot ◽  
Traffic Sign ◽  
Traffic Signs ◽  
High Level ◽  
Anchor Design

Detecting and classifying real-life small traffic signs from large input images is difficult due to their occupying fewer pixels relative to larger targets. To address this challenge, we proposed a deep-learning-based model (Dense-RefineDet) that applies a single-shot, object-detection framework (RefineDet) to maintain a suitable accuracy–speed trade-off. We constructed a dense connection-related transfer-connection block to combine high-level feature layers with low-level feature layers to optimize the use of the higher layers to obtain additional contextual information. Additionally, we presented an anchor-design method to provide suitable anchors for detecting small traffic signs. Experiments using the Tsinghua-Tencent 100K dataset demonstrated that Dense-RefineDet achieved competitive accuracy at high-speed detection (0.13 s/frame) of small-, medium-, and large-scale traffic signs (recall: 84.3%, 95.2%, and 92.6%; precision: 83.9%, 95.6%, and 94.0%). Moreover, experiments using the Caltech pedestrian dataset indicated that the miss rate of Dense-RefineDet was 54.03% (pedestrian height > 20 pixels), which outperformed other state-of-the-art methods.

scholarly journals Photonic welding points for arbitrary on-chip optical interconnects

Nanophotonics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 1679-1686 ◽  
Author(s):  
Zejie Yu ◽  
Yang Ma ◽  
Xiankai Sun
Keyword(s):  
Integrated Circuits ◽  
Low Loss ◽  
Photonic Networks ◽  
New Approach ◽  
Waveguide Bends ◽  
Arbitrary Configuration ◽  
Integration Density ◽  
On Chip ◽  
Insertion Losses ◽  
Further Development

AbstractPhotonic integrated circuits (PICs) are an ideal platform for chip-scale computation and communication. To date, the integration density remains an outstanding problem that limits the further development of PIC-based photonic networks. Achieving low-loss waveguide routing with arbitrary configuration is crucial for both classical and quantum photonic applications. To manipulate light flows on a chip, the conventional wisdom relies on waveguide bends of large bending radii and adiabatic mode converters to avoid insertion losses from radiation leakage and modal mismatch, respectively. However, those structures usually occupy large footprints and thus reduce the integration density. To overcome this difficulty, this work presents a fundamentally new approach to turn light flows arbitrarily within an ultracompact footprint. A type of “photonic welding points” joining two waveguides of an arbitrary intersecting angle has been proposed and experimentally demonstrated. These devices with a footprint of less than 4 μm2can operate in the telecommunication band over a bandwidth of at least 140 nm with an insertion loss of less than 0.5 dB. Their fabrication is compatible with photonic foundry processes and does not introduce additional steps beyond those needed for the waveguides. Therefore, they are suitable for the mass production of PICs and will enhance the integration density to the next level.

Porous low dielectric constant materials for microelectronics

2005 ◽  
Vol 364 (1838) ◽  
pp. 201-215 ◽  
Author(s):  
Mikhail R Baklanov ◽  
Karen Maex
Keyword(s):  
Dielectric Constant ◽  
High Speed ◽  
Large Scale ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Large Scale Integration ◽  
The Subject ◽  
On Chip ◽  
Scale Integration ◽  
Selection Of

Materials with a low dielectric constant are required as interlayer dielectrics for the on-chip interconnection of ultra-large-scale integration devices to provide high speed, low dynamic power dissipation and low cross-talk noise. The selection of chemical compounds with low polarizability and the introduction of porosity result in a reduced dielectric constant. Integration of such materials into microelectronic circuits, however, poses a number of challenges, as the materials must meet strict requirements in terms of properties and reliability. These issues are the subject of the present paper.

scholarly journals The development of real-time communication network based on Zigbee and Ethernet for Photovoltaic systems

2014 ◽  
Vol 17 (1) ◽  
pp. 5-15
Author(s):  
Dung Quoc Phan ◽  
Dat Ngoc Dao ◽  
Hiep Chi Le
Keyword(s):  
Communication Network ◽  
Real Time ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Photovoltaic System ◽  
Solar Inverter ◽  
Ethernet Controller ◽  
Controller Board ◽  
High Level

In a large system with a lot of distribution solar sources which are all connected to the national grid, a communication system becomes the important part for data acquisition in order to control the whole system stable and efficiency. To deal with this challenge, this paper presents a solution based on Zigbee and Ethernet communication standard. Zigbee standard was created to be a specification of a high level wireless communication protocol which is not only secure, reliable, simple but also low cost and low power. With Zigbee, we can create a communication network for hundreds to thousands of mini solar sources in a large scale of photovoltaic system. Ethernet is a high speed wired communication technology that is used widely in industrial and automatic applications. Together Zigbee and Ethernet bring to us a real-time communication solution for the system. In the experiment prototype of this paper, we use the CC2530ZNP-Mini Kit to create a simple network includes one coordinate and one end device for the first step. The end device was configured to get current and voltage values from a 3-phase grid-connected solar inverter 800Wpk and then sends the values to the coordinate. After the coordinate received data, it would send them to an Ethernet controller board. To display the data through Ethernet, we embedded a web server on the Ethernet controller board. By this way, the data was easy to visualize and supervised by using any web browser.

EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES

2013 ◽  
Vol 22 (04) ◽  
pp. 1350025
Author(s):  
STAVROS P. DOKOUZYANNIS ◽  
ARGIRIS P. MOKIOS
Keyword(s):  
Systolic Array ◽  
High Speed ◽  
Large Scale ◽  
Logic Synthesis ◽  
Evaluation Study ◽  
Optimization Approach ◽  
Array Processors ◽  
Field Programmable ◽  
High Level ◽  
Selection Of

This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projection Vectors (PVs) and Task Scheduling Vectors (TSVs) on the optimization process. Two optimization approaches are examined, namely technology mapping using FlowMap and Flowpack algorithms and optimization via logic synthesis using Xilinx Synthesis Tool. The multiplication of matrices, with entries being up to 32-bit integer vectors, has been taken as a sample space for the experiments conducted. The results, confirm that the selection of PV and TSV greatly affects the number of input/output signal connections of the FPGA, while the selection of an optimization approach affects the final number of logic resources occupied on the targeted device.

scholarly journals On-chip scalable mode-selective converter based on asymmetrical micro-racetrack resonators

Nanophotonics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1447-1455
Author(s):  
Huifu Xiao ◽  
Zhenfu Zhang ◽  
Junbo Yang ◽  
Xu Han ◽  
Wenping Chen ◽  
...  
Keyword(s):  
Large Scale ◽  
Optical Network ◽  
Monochromatic Light ◽  
Network On Chip ◽  
Silicon On Insulator ◽  
Intelligent Network ◽  
Silicon Waveguides ◽  
Mode Division Multiplexing ◽  
Potential Applications ◽  
On Chip

AbstractMode division multiplexing (MDM) technology has been well known to researchers for its ability to increase the link capacity of photonic network. While various mode processing devices were demonstrated in recent years, the reconfigurability of multi-mode processing devices, which is vital for large-scale multi-functional networks, is rarely developed. In this paper, we first propose and experimentally demonstrate a scalable mode-selective converter using asymmetrical micro-racetrack resonators (MRRs) for optical network-on-chip. The proposed device, composed of cascaded MRRs, is able to convert the input monochromatic light to an arbitrary supported mode in the output waveguide as required. Thermo-optical effect of silicon waveguides is adopted to tune the working states of the device. To test the utility, a device for proof-of-concept is fabricated and experimentally demonstrated based on silicon-on-insulator substrate. The measured spectra of the device show that the extinction ratios of MRRs are larger than 18 dB, and modal crosstalk for selected modes are all less than −16.5 dB. The switching time of the fabricated device is in the level of about 40 μs. The proposed device is believed to have potential applications in multi-functional and intelligent network-on-chip, especially in reconfigurable MDM networks.

System-on-Chip Design of the Whirlpool Hash Function

2008 ◽  
pp. 256-270
Author(s):  
Paris Kitsos
Keyword(s):  
Hash Function ◽  
High Speed ◽  
Large Scale ◽  
System On Chip ◽  
Security Level ◽  
Chip Design ◽  
Silicon Area ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

In this chapter, a system-on-chip design of the newest powerful standard in the hash families, named Whirlpool, is presented. With more details an architecture and two very large-scale integration (VLSI) implementations are presented. The first implementation is suitable for high speed applications while the second one is suitable for applications with constrained silicon area resources. The architecture permits a wide variety of implementation tradeoffs. Different implementations have been introduced and each specific application can choose the appropriate speed-area, trade-off implementation. The implementations are examined and compared in the security level and in the performance by using hardware terms. Whirlpool with RIPEMD, SHA-1, and SHA-2 hash functions are adopted by the International Organization for Standardization (ISO/IEC, 2003) 10118-3 standard. The Whirlpool implementations allow fast execution and effective substitution of any previous hash families’ implementations in any cryptography application.

scholarly journals Multi-Optical Network-on-Chip for Large Scale MPSoC

2010 ◽  
Vol 2 (3) ◽  
pp. 77-80 ◽  
Author(s):  
Sebastien Le Beux ◽  
Jelena Trajkovic ◽  
Ian O'Connor ◽  
Gabriela Nicolescu ◽  
Guy Bois ◽  
...  
Keyword(s):  
Large Scale ◽  
Optical Network ◽  
Network On Chip ◽  
On Chip

scholarly journals Silicon Photonic Mode-Division Reconfigurable Optical Add/Drop Multiplexers with Mode-Selective Integrated MEMS Switches

Photonics ◽  
2020 ◽  
Vol 7 (4) ◽  
pp. 80
Author(s):  
Vinh Huu Nguyen ◽  
In Ki Kim ◽  
Tae Joon Seok
Keyword(s):  
Optical Networks ◽  
Large Scale ◽  
Laser Source ◽  
Mems Switches ◽  
Silicon Photonic ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Micro Electromechanical System ◽  
Insertion Losses

Mode-division multiplexing (MDM) is an attractive solution for future on-chip networks to enhance the optical transmission capacity with a single laser source. A mode-division reconfigurable optical add/drop multiplexer (ROADM) is one of the key components to construct flexible and complex on-chip optical networks for MDM systems. In this paper, we report on a novel scheme of mode-division ROADM with mode-selective silicon photonic MEMS (micro-electromechanical system) switches. With this ROADM device, data carried by any mode-channels can be rerouted or switched at an MDM network node, i.e., any mode could be added/dropped to/from the multimode bus waveguide flexibly and selectively. Particularly, the design and simulation of adiabatic vertical couplers for three quasi-TE modes (TE0, TE1, and TE2 modes) based on effective index analysis and mode overlap calculation method are reported. The calculated insertion losses are less than 0.08 dB, 0.19 dB, and 0.03 dB for the TE0 mode, TE1 mode, and TE2 mode couplers, respectively, over a wavelength range of 75 nm (1515–1590 nm). The crosstalks are below −20 dB over the bandwidth. The proposed device is promising for future on-chip optical networks with flexible functionality and large-scale integration.

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