Porous low dielectric constant materials for microelectronics

2005 ◽  
Vol 364 (1838) ◽  
pp. 201-215 ◽  
Author(s):  
Mikhail R Baklanov ◽  
Karen Maex
Keyword(s):  
Dielectric Constant ◽  
High Speed ◽  
Large Scale ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Large Scale Integration ◽  
The Subject ◽  
On Chip ◽  
Scale Integration ◽  
Selection Of

Materials with a low dielectric constant are required as interlayer dielectrics for the on-chip interconnection of ultra-large-scale integration devices to provide high speed, low dynamic power dissipation and low cross-talk noise. The selection of chemical compounds with low polarizability and the introduction of porosity result in a reduced dielectric constant. Integration of such materials into microelectronic circuits, however, poses a number of challenges, as the materials must meet strict requirements in terms of properties and reliability. These issues are the subject of the present paper.

On Advanced Interconnect Using Low Dielectric Constant Materials as Inter-Level Dielectrics

1996 ◽  
Vol 427 ◽  
Author(s):  
Bin Zhao ◽  
Shi-Qing Wang ◽  
Steven Anderson ◽  
Robbie Lam ◽  
Marcy Fiebig ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
High Speed ◽  
Organic Materials ◽  
Chemical Vapor ◽  
Evaluation Methodology ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Integration Architecture ◽  
Low Dielectric Constant Materials ◽  
On Chip

AbstractIn high performance integrated circuits, low dielectric constant (low-ε) materials are required as inter-level dielectric (ILD) for on-chip interconnect to provide advantages in high speed, low dynamic power dissipation and low cross-talk noise. A variety of low dielectric constant materials, which include fluorinated silicon-oxide, porous silica and porous organic materials, chemical vapor deposited and spin-on deposited (SOD) organic materials, have been developed or are under development to fulfill this need. In this paper, we first review the need and integration architecture of low-ε materials for on-chip interconnect. Then, we discuss the consequence of using low-ε materials as ILD in advanced interconnect with emphasis on the ILD electrical characteristics and the interconnect reliability. Although the focus is on several new promising SOD low-ε materials, the developed evaluation methodology is applicable to other type low-ε materials as well.

Comparative Study of Low Dielectric Constant Material Deposited Using Different Precursors

2011 ◽  
Vol 233-235 ◽  
pp. 2480-2485
Author(s):  
Yi Lung Cheng ◽  
Yi Shiung Lu ◽  
Tai Jung Chiu
Keyword(s):  
Thermal Stability ◽  
Vapor Deposition ◽  
Large Scale ◽  
Dielectric Material ◽  
Chemical Vapor ◽  
Electrical Performance ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Large Scale Integration ◽  
Scale Integration

Two kinds of organosilicate precursors, trimethylsilane (3MS) and diethoxymethylsilane (DEMS), were used to produce low-k films by plasma-enhanced chemical vapor deposition (PECVD) in this work. The experimental results indicate that DEMS-based low-k films have superior electrical performance and better thermal stability as compared to 3MS-based low-k films. Therefore, DEMS-based films are the promising low-k materials which can be integrated in very large scale integration circuit as an inter-layer dielectric material.

System-on-Chip Design of the Whirlpool Hash Function

2008 ◽  
pp. 256-270
Author(s):  
Paris Kitsos
Keyword(s):  
Hash Function ◽  
High Speed ◽  
Large Scale ◽  
System On Chip ◽  
Security Level ◽  
Chip Design ◽  
Silicon Area ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

In this chapter, a system-on-chip design of the newest powerful standard in the hash families, named Whirlpool, is presented. With more details an architecture and two very large-scale integration (VLSI) implementations are presented. The first implementation is suitable for high speed applications while the second one is suitable for applications with constrained silicon area resources. The architecture permits a wide variety of implementation tradeoffs. Different implementations have been introduced and each specific application can choose the appropriate speed-area, trade-off implementation. The implementations are examined and compared in the security level and in the performance by using hardware terms. Whirlpool with RIPEMD, SHA-1, and SHA-2 hash functions are adopted by the International Organization for Standardization (ISO/IEC, 2003) 10118-3 standard. The Whirlpool implementations allow fast execution and effective substitution of any previous hash families’ implementations in any cryptography application.

Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS

2009 ◽  
Vol 6 (1) ◽  
pp. 38-41
Author(s):  
Lewis Dove
Keyword(s):  
Integrated Circuits ◽  
High Frequency ◽  
High Speed ◽  
Large Scale ◽  
Flip Chip ◽  
Data Converters ◽  
Mixed Signal ◽  
Large Scale Integration ◽  
Circuit Techniques ◽  
Scale Integration

Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.

Self-Adaptive SoCs for Dependability

2014 ◽  
pp. 1-21
Author(s):  
Liang Guang ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
Large Scale ◽  
Future Research ◽  
Great Promise ◽  
Primary Concern ◽  
Technology Scaling ◽  
Computing Paradigm ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Self Adaptive

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

Energy-Aware Switch Design

2013 ◽  
pp. 341-360 ◽  
Author(s):  
Yukihiro Nakagawa ◽  
Takeshi Shimizu ◽  
Takeshi Horie ◽  
Yoichi Koyanagi ◽  
Osamu Shiraki ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Single Chip ◽  
Energy Aware ◽  
It Industry ◽  
Gigabit Ethernet ◽  
Switch Architecture ◽  
Large Scale Integration ◽  
Scale Integration

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. Virtualized commodity servers are scaled out in the data center and increase the demand for bandwidth between servers. Therefore, a high performance switch is required. The shared-memory switch is the best performance/cost switch architecture, but it is challenging to satisfy the requirements on the memory bandwidth in a high speed network. In addition, it is challenging to handle variable-length frames in Ethernet. This chapter describes the main challenges in Ethernet switch designs and then energy-aware switch designs, including switch architecture and high speed IO interface. As implementation examples, this chapter also describes a single-chip switch Large Scale Integration (LSI) embedded with high-speed IO interfaces and 10-Gigabit Ethernet (10GbE) switch blade equipped with the switch LSI. The switch blade delivers 100% more performance per watt than other 10GbE switch blades in the industry.

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