scholarly journals DESIGN OF A 500MHZ, 4-BIT LOW POWER ADC FOR UWB APPLICATION

2014 ◽  
pp. 81-86
Author(s):  
SANTOSH KUMAR PATNAIK ◽  
DR. SWAPNA BANERJEE
Keyword(s):  
Power Consumption ◽  
Input Signal ◽  
Power Supply ◽  
Cmos Technology ◽  
Sampling Frequency ◽  
Total Power ◽  
Digital Converter ◽  
Analog To Digital ◽  
Total Power Consumption ◽  
Single Power

This paper presents a new topology of an Analog-to-Digital Converter (ADC), named as Switched Reference ADC (SR-ADC) where the reference voltages are applied through switches. The switched reference voltage concept works with few mutually exclusive switches which are appropriately selecting the reference voltages for comparison with the input signal. This SR-ADC has been implemented using 0.18μm single poly and six metal CMOS technology. The spectra simulation result of this SR-ADC shows an ENOB of ≈3.53 for a 1V peak-to-peak input signal having a frequency of 100MHz while operating at a sampling frequency of 500MHz. The total power consumption is 21.39mW for a single power supply of 1.8V having a core area of ≈253μm*221μm.

scholarly journals ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

2019 ◽  
Vol 8 (3) ◽  
Author(s):  
Arash Rezapour ◽  
Mohammad Bagher Tavakoli ◽  
Farbod Setoudeh
Keyword(s):  
Power Supply ◽  
Data Transfer ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Analysis And Design ◽  
Second Stage ◽  
Total Power Consumption

A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stage is not used the amplifier and instead the buffer is used for data transfer to the second stage. The speed of this converter is 350MS/s. An amplifier circuit with accurate gain of 6 and a very accurate unit gain buffer circuit that are open loop with a new structure were. used. In this Converter, the first 3 bits are extracted simultaneously with sampling. The proposed analog-to-digital converter was designed with the total power consumption 75mW using power supply of 1.8v.

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

scholarly journals EVALUATION OF ADDITIONAL LOSSES AND EFFICIENCY ELECTRICITY CONSUMPTION REGULATION IN LOCAL POWER SUPPLY SYSTEMS

2020 ◽  
pp. 7-21
Author(s):  
S. Denysiuk ◽  
T. Bazyuk
Keyword(s):  
Power Consumption ◽  
Electric Power ◽  
Power Supply ◽  
Electricity Consumption ◽  
Total Power ◽  
Local Power ◽  
Higher Harmonics ◽  
Total Power Consumption ◽  
Supply Systems ◽  
Additional Losses

Peculiarities of estimation of total energy losses in electric networks and estimation of nature of electricity consumption in local power supply systems (LES) are given. The structure of additional electricity losses in LES in the presence of higher harmonics of current and voltage is carried out, the generalized schedule of instantaneous functions of current i(t), voltage u(t), and power p(t) on components. The offered indicators of an estimation of the performance of criterion of a minimum of losses of the electric power in LES allow to estimate levels of distortion of power processes at consideration both exchange processes, and at the analysis of additional losses of the electric power. The accuracy of measuring the integrated characteristics of energy exchange depending on the available levels of distortion of voltage and current signals is considered. It is shown that in order to take into account the influence of higher harmonics on the total power consumption, it is necessary to determine the change of Frize QFpower as an indicator of additional electricity losses in the presence of non-sinusoidal currents and voltages in at different ratios between the value of current and voltage of the first and higher harmonics. The evaluation of the efficiency of power consumption regulation using the Frize QF power at an arbitrary time interval, as well as the corresponding current distribution into active and reactive components are considered. The peculiarities of increasing the efficiency of power consumption regulation in LES at the cyclic change of generator parameters and load are analysed.

scholarly journals 60 GHz Front-End Components for Broadband Wireless Communication in 130 nm CMOS Technology

2016 ◽  
Vol 21 (1) ◽  
pp. 67-77
Author(s):  
Vasilis Kolios ◽  
Konstantinos Giannakidis ◽  
Grigorios Kalivas
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Spectral Space ◽  
60 Ghz ◽  
Front End ◽  
Total Power Consumption ◽  
5 Ghz

Abstract The over 5 GHz available spectral space allocated worldwide around the 60 GHz band, is very promising for very high data rate wireless short-range communications. In this article we present two key components for the 60 GHz front-end of a transceiver, in 130 nm RF CMOS technology: a single-balanced mixer with high Conversion Gain (CG), reduced Noise Figure (NF) and low power consumption, and an LC cross-coupled Voltage Controlled Oscillator (VCO) with very good linearity, with respect to Vctrl, and very low Phase Noise (PN). In both circuits, custom designed inductors and a balun structure for the mixer are employed, in order to enhance their performance. The VCO’s inductor achieves an inductance of 198 pH and a quality factor (Q) of 30, at 30 GHz. The balun shows less than 1o Phase Imbalance (PI) and less than 0.2 dB Amplitude Imbalance (AI), from 57 to 66 GHz. The mixer shows a CG greater than 15 dB and a NF lower than 12 dB. In addition, the VCO achieves a Phase Noise lower than -106 dBc/Hz at 1 MHz offset, and shows great linearity for the entire band. Both circuits are biased with a 1.2 V supply voltage and the total power consumption is about 10.6 mW for the mixer and 10.92 mW for the VCO.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740051 ◽  
Author(s):  
Yunfeng Hu ◽  
Chao Xiong ◽  
Bin Li
Keyword(s):  
Power Supply ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Area Reduction ◽  
Area Efficient

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

scholarly journals A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter

2021 ◽  
Author(s):  
Shahab Ardalan
Keyword(s):  
Power Dissipation ◽  
Low Voltage ◽  
Low Power Design ◽  
Cmos Technology ◽  
Total Power ◽  
Cable Modem ◽  
Analog To Digital Converter ◽  
Flat Panel Display ◽  
Digital Converter ◽  
Analog To Digital

A 1.2 V, 8 bit, 100 MSample/Sec Pipeline Analog-to-Digital Converter is designed in 0.18-μm standard CMOS technology. An emphasis was placed on observing the low voltage and low power design. The architecture of this ADC is 1 bit/stage pipelined configuration. With above specifications the designed ADC can be applicable for DVI flat-panel display; Giga bit Ethernet on copper, RGB to LCD converter and cable modem. This designed ADC can achieve SNDR 56dB in 100 MHz sampling frequency with 8 bit resolution. Total power dissipation is 40.6mW and INL is around 1 LSB and the maximum swing of the input is 1 Volt peak to peak which is almost rail-to-rail situation. The core area of the ADC excluding pads is around 0.25mm 2 .

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

scholarly journals A TRANSISTOR LEVEL ANALYSIS FOR A 8-BIT VEDIC MULTIPLIER

2012 ◽  
pp. 78-83
Author(s):  
ARUN K PATRO ◽  
KUNAL N DEKATE
Keyword(s):  
Power Consumption ◽  
Digital Signal ◽  
Cmos Technology ◽  
Total Power ◽  
Vedic Multiplier ◽  
Total Power Consumption ◽  
Improved Performance ◽  
Almost All ◽  
Signal Processors ◽  
Level Analysis

Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "Urdhvatiryakbhyam sutra" , which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. The design is then verified in T-SPICE using 0.18 um CMOS technology library file. The analysis is made for various voltages across a range of 2.5V to 5V, to validate the design. A CMOS digital multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed multiplier consumes 80% less power compared to the gate level analysis done earlier. The core area of the proposed multiplier is 737 um2 . Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.

scholarly journals Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS

2012 ◽  
pp. 89-93
Author(s):  
Pradeep Kumar ◽  
Amit Kolhe
Keyword(s):  
Power Consumption ◽  
Response Time ◽  
Low Power ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Chip Area ◽  
Flash Adc ◽  
Analog To Digital ◽  
Design And Implementation

This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

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