Flash Memory Scaling

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 814-817 ◽  
Author(s):  
Al Fazio
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Three Dimensional ◽  
Memory Cell ◽  
Current Status ◽  
Memory Cells ◽  
Technology Scaling ◽  
Complex Structural ◽  
High Dielectric

AbstractIn order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films used today in memory cells. Likewise, planar-based memory cell scaling is approaching the point where scaling constraints force exploration of new materials and nonplanar, three-dimensional scaling alternatives. This article will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor floating-gate-based nonvolatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor-based flash memory cells can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. More complex, structural innovations will be required to achieve further scaling.

Future Directions of Non-volatile Memory Technologies

2004 ◽  
Vol 830 ◽  
Author(s):  
Albert Fazio
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
Memory Cell ◽  
Current Status ◽  
Technology Scaling ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Complex Structural ◽  
Flash Memory Cell ◽  
To Come

ABSTRACTIt expected that for many years to come, the majority of the nonvolatile memories shipped will be based on current mainstream flash technologies, which utilize transistor based charge storage memory cells and multi-level-cell concepts, for storing more than one logic bit in a single physical cell. Moore's law will continue to drive transistor based memory technology scaling but technology complexity will be increasing. In order to meet technology scaling, the mainstream transistor based flash technologies will start evolving to incorporate material and structural innovations. This paper will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor based non-volatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor based flash memory cell can scale into the 32nm node. Further, more complex, structural innovations will be required to maintain further scaling. New memory concepts, not relying on transistors as a basis of the memory cell, provide new opportunities for future low cost memories. Several of these new concepts will be summarized and contrasted with the mainstream transistor based flash memory technologies.

CARBON NANOTUBE BASED NONVOLATILE MEMORY DEVICES

2006 ◽  
Vol 16 (04) ◽  
pp. 959-975 ◽  
Author(s):  
YUEGANG ZHANG
Keyword(s):  
Carbon Nanotube ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Memory Device ◽  
Floating Gate ◽  
Memory Devices ◽  
Memory Cells ◽  
Nonvolatile Memory Devices ◽  
Electrostatic Coupling

The technology progress and increasing high density demand have driven the nonvolatile memory devices into nanometer scale region. There is an urgent need of new materials to address the high programming voltage and current leakage problems in the current flash memory devices. As one of the most important nanomaterials with excellent mechanical and electronic properties, carbon nanotube has been explored for various nonvolatile memory applications. While earlier proposals of "bucky shuttle" memories and nanoelectromechanical memories remain as concepts due to fabrication difficulty, recent studies have experimentally demonstrated various prototypes of nonvolatile memory cells based on nanotube field-effect-transistor and discrete charge storage bits, which include nano-floating gate memory cells using metal nanocrystals, oxide-nitride-oxide memory stack, and more simpler trap-in-oxide memory devices. Despite of the very limited research results, distinct advantages of high charging efficiency at low operation voltage has been demonstrated. Single-electron charging effect has been observed in the nanotube memory device with quantum dot floating gates. The good memory performance even with primitive memory cells is attributed to the excellent electrostatic coupling of the unique one-dimensional nanotube channel with the floating gate and the control gate, which gives extraordinary charge sensibility and high current injection efficiency. Further improvement is expected on the retention time at room temperature and programming speed if the most advanced fabrication technology were used to make the nanotube based memory cells.

scholarly journals Estimation of Ge nanocrystals size by Raman, X-rays, and HRTEM techniques

2008 ◽  
Vol 14 (S3) ◽  
pp. 61-64 ◽  
Author(s):  
S.R.C. Pinto ◽  
P. Caldelas ◽  
A.G. Rolo ◽  
A. Chahboun ◽  
M.J.M. Gomes
Keyword(s):  
Flash Memory ◽  
Nonvolatile Memory ◽  
High Dielectric Constant ◽  
Memory Systems ◽  
X Rays ◽  
Processing Conditions ◽  
Flash Memories ◽  
Potential Applications ◽  
High Dielectric ◽  
Ge Nanocrystals

Ge NCs have attracted considerable attention because of their potential applications in nonvolatile memory and integrated optoelectronics. A number of groups have already proposed integrate flash memories based on Ge NCs embedded SiO2 matrix. Since Al2O3 presents a high dielectric constant comparatively to SiO2, it is a good candidate to replace silica in flash memory systems, and therefore improve their performances. Moreover, Al2O3 presents good mechanical properties, and supports high temperature, which leads it to be an ideal material for Si processing conditions. However, a few studies have been reported on Ge NCs embedded in Al2O3 matrix.

A Novel PHINES Flash Memory Cell with Low Power Program/Erase, Small Pitch, Two-Bits-Per-Cell for Data Storage Applications

2005 ◽  
Vol 52 (4) ◽  
pp. 541-546 ◽  
Author(s):  
C.-C. Yeh ◽  
T. Wang ◽  
W.-J. Tsai ◽  
T.-C. Lu ◽  
M.-S. Chen ◽  
...  
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Flash Memory ◽  
Memory Cell ◽  
Small Pitch ◽  
Flash Memory Cell

Thermal Conductivity Measurements and Modeling of Phase-Change GST Materials

2007 ◽  
Author(s):  
Yizhang Yang ◽  
Taehee Jeong ◽  
Hendrik F. Hamann ◽  
Jimmy Zhu ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Conductivity ◽  
Phase Change ◽  
Data Storage ◽  
Flash Memory ◽  
Performance Optimization ◽  
Phase Change Materials ◽  
Memory Cell ◽  
Data Access ◽  
Optical Recording ◽  
Access Time

Phase-change technology has been widely used in rewritable disks for optical recording applications. Recently, it has also received attention as a candidate for future high storage density non-volatile random access memory, due to its much longer cycle life (∼1013) and fast data access time (∼100ns) compared with the existing Flash memory technology. In this paper, we present thermal conductivity data and models for phase-change GeSbTe material that would be helpful in performance optimization and improvement in the reliability (i.e., enhancement of data rate, cyclability, control of mark-edge jitter) of phase-change-based data storage devices and systems. We perform the thermal characterization of Ge4Sb1Te5 and Ge2Sb2Te5 phase-change materials for the application of optical recording and phase-change memory cell using the techniques of thermoreflectance and electrical resistance thermometry. The limits of lattice and electronic thermal conductivities are investigated to determine their relative contributions as a function of tellurium concentration at different crystalline structures.

Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

2007 ◽  
Vol 997 ◽  
Author(s):  
Torsten Mueller ◽  
C. Kleint ◽  
C. Fitz ◽  
M. Isler ◽  
S. Riedel ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Cell ◽  
Small Cell ◽  
Gate Length ◽  
Memory Cells ◽  
Thermal Budget ◽  
Key Features ◽  
Flash Memory Cell ◽  
Charge Trapping Memory

AbstractA 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.

A novel tri-control gate surrounding gate transistor (TCG-SGT) nonvolatile memory cell for flash memory

2006 ◽  
Vol 50 (6) ◽  
pp. 924-928 ◽  
Author(s):  
Takuya Ohba ◽  
Hiroki Nakamura ◽  
Hiroshi Sakuraba ◽  
Fujio Masuoka
Keyword(s):  
Flash Memory ◽  
Nonvolatile Memory ◽  
Memory Cell ◽  
Surrounding Gate

scholarly journals MODELING OF NONVOLATILE MEMORY CELL WITH OPTICAL CONTROLLING

2020 ◽  
Author(s):  
Mikhail Makarov ◽  
Alexander Sapegin ◽  
Dmitry Korolev
Keyword(s):  
Chalcogenide Glass ◽  
Nonvolatile Memory ◽  
Optical Memory ◽  
Memory Cell ◽  
Optical Control ◽  
Glass Film ◽  
Memory Cells ◽  
Original Shape ◽  
Switching Memory

This paper represents results of modeling nonvolatile memory cells with optical controlling. Modeling of waveguides locally loaded with a GeSbTe (GST) chalcogenide glass film has been carried out. Based on calculations of the JMAK model, the original shape of optical memory pulses with optical control is proposed, which makes it possible to reduce the time spent on switching memory.

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