Development of 3D-Packaging Process Technology for Stacked Memory Chips

2006 ◽  
Vol 970 ◽  
Author(s):  
Toshiro Mitsuhashi ◽  
Yoshimi Egawa ◽  
Osamu Kato ◽  
Yoshihiro Saeki ◽  
Hidekazu Kikuchi ◽  
...  
Keyword(s):  
Back Side ◽  
Electrical Characteristics ◽  
Process Technology ◽  
Through Silicon Via ◽  
Packaging Technology ◽  
Packaging Process ◽  
Side Process ◽  
3D Packaging ◽  
Stacked Memory

ABSTRACTA 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.

Multipurpose quick 3D packaging process

2011 ◽  
Author(s):  
Zhao Yongrui ◽  
Ma Hongbo ◽  
Bi Minglu ◽  
Huang Zhanwu ◽  
Jia Jun ◽  
...  
Keyword(s):  
Packaging Process ◽  
3D Packaging

Fine‐pitch through‐silicon via integration with self‐aligned back‐side benzocyclobutene passivation layer

2016 ◽  
Vol 11 (10) ◽  
pp. 619-622 ◽  
Author(s):  
Yong Guan ◽  
Shenglin Ma ◽  
Qinghua Zeng ◽  
Jing Chen ◽  
Yufeng Jin
Keyword(s):  
Passivation Layer ◽  
Back Side ◽  
Through Silicon Via ◽  
Fine Pitch

Bonding Technologies for 3D integration

2015 ◽  
Vol 2015 (1) ◽  
pp. 000231-000234
Author(s):  
Sascha Lohse ◽  
Alexander Wollanke
Keyword(s):  
Flip Chip ◽  
Process Technology ◽  
3D Integration ◽  
Test Procedures ◽  
Fine Pitch ◽  
Ic Packaging ◽  
Die Stacking ◽  
3D Packaging ◽  
Small Bump ◽  
Suitable Process

Tougher requirements related to the request for smaller, lighter and multi-functional electronic devices impose increased demands on IC packaging. Ever more complex circuitry, fine pitch and micro bump designs and die stacking are examples of how the industry meets these demands. Finding a suitable process technology for 3D packaging can be a challenge. This paper provides information about various connection methods predominantly used in today's 3D packaging. In comprehensive trials, various dies characterized by high bump count (up to 143,000), fine pitch (down to 25 μm) and small bump diameter (down to 13 μm) were placed on a substrate using a semi-automated flip chip bonder. This whitepaper describes test procedures for different 3D integration technologies and presents utilized process parameters and results.

Si Vapor Chamber Integrated with Through Silicon Via for 3D Packaging

2013 ◽  
Vol 2013 (1) ◽  
pp. 000552-000557 ◽  
Author(s):  
Jun Taniguchi ◽  
Takeshi Shioga ◽  
Yoshihiro Mizuno
Keyword(s):  
Thermal Resistance ◽  
Heat Dissipation ◽  
Working Fluid ◽  
In Situ Observation ◽  
Vapor Chamber ◽  
Cover Glass ◽  
Through Silicon Via ◽  
Improvement Rate ◽  
Fine Pitch ◽  
3D Packaging

We demonstrate an etched silicon vapor chamber integrated with a through-silicon via (TSV) for 3D packaging. The Si vapor chamber chip enables low mismatch in the thermal expansion coefficient of a Si-LSI chip and provides a new heat dissipation path for 3D-LSI inter layer cooling. For the first prototype of the vapor chamber, an outside 33-mm × 33-mm chip consisting of a 25-mm × 25-mm area for the vapor chamber, a wick structure 30-μm high, and a vapor passage 100-μm high is developed. In-situ observation of the behavior of the working fluid through the cover glass and heat transfer enhancement is successfully demonstrated. The improvement rate of thermal resistance is 7.1% compared to a test chip without working fluid. Next, the fluid flow of a second vapor chamber prototype consisting of the first prototype integrated with a TSV structure using a Si pillar of 150-μm diameter is investigated. Thermal resistance and droplet observation conducted to evaluate the influence of the TSV. The operation of the vapor chamber is confirmed when a Si pillar is arranged to a coarse pitch of more than 500 μm. A droplet is generated and the vapor passage is partially obstructed. However, the droplet eventually degenerated and the performance of the vapor chamber is maintained. When the Si pillar is arranged to a fine pitch of 200 μm, the entire vapor passage is blocked during the liquid charging process, and no improvement is observed in the thermal resistance of the chip.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

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