Defect Reduction and Its Mechanism of Selective Ge Epitaxy in Trenches on Si(001) Substrates Using Aspect Ratio Trapping

AbstractDefect-free germanium has been demonstrated in SiO2 trenches on silicon via aspect ratio trapping, whereby defects arising from lattice mismatch are trapped by laterally confining sidewalls. Results were achieved through a combination of conventional photolithography, reactive ion etching of SiO2, and selective growth of Ge as thin as 450 nm. It was revealed that facets, when formed early on in the growth process, play a dominant role in determining the configurations of threading dislocations in the films. This approach shows great promise for the integration of Ge and/or III-V materials, sufficiently large for key device applications, onto silicon substrates.

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Two-step Defect Reduction of GaAs/Si Epitaxy by Selective Aspect Ratio Trapping

MRS Proceedings ◽

10.1557/proc-1030-g06-17 ◽

2007 ◽

Vol 1030 ◽

Cited By ~ 1

Author(s):

Jizhong Li ◽

J. Bai ◽

C. Major ◽

M. Carroll ◽

A. Lochtefeld ◽

...

Keyword(s):

Aspect Ratio ◽

Defect Formation ◽

Lattice Mismatch ◽

Defect Density ◽

Layer Growth ◽

Threading Dislocations ◽

Cross Sectional ◽

Defect Reduction ◽

Plan View ◽

Step Defect

AbstractWe report on the MOCVD growth of GaAs on patterned Si utilizing the Aspect Ratio Trapping (ART) method to reduce threading dislocations resulting from lattice mismatch. Defect-free GaAs was obtained from growth in sub-micron trenches formed in SiO2 on Si (001) substrates. Material quality has been characterized by cross-sectional and plan-view TEM and XRD. It was found that when growing GaAs above the trenched region, coalescence-induced threading dislocations (TDs) and planar defects were introduced at the coalescence junction interfaces. These defects were found to be unrelated to the misfit defects (MDs) on GaAs/Si interface that originated during initial epitaxial growth. Causes of coalescence defect formation were experimentally investigated by employing a two-step defect reduction scheme. It is concluded that by further optimizing growth conditions during coalesce layer growth, low defect-density GaAs material can be obtained on Si substrate.

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Metamorphic Integration of GaInAsSb Material on GaAs Substrates for Light Emitting Device Applications

Materials ◽

10.3390/ma12111743 ◽

2019 ◽

Vol 12 (11) ◽

pp. 1743

Author(s):

Qi Lu ◽

Andrew Marshall ◽

Anthony Krier

Keyword(s):

Quantum Wells ◽

Buffer Layer ◽

Lattice Mismatch ◽

Cost Effective ◽

Threading Dislocations ◽

Cross Sectional ◽

Light Emitting ◽

Light Emitting Devices ◽

Gaas Substrates ◽

Device Applications

The GaInAsSb material has been conventionally grown on lattice-matched GaSb substrates. In this work, we transplanted this material onto the GaAs substrates in molecular beam epitaxy (MBE). The threading dislocations (TDs) originating from the large lattice mismatch were efficiently suppressed by a novel metamorphic buffer layer design, which included the interfacial misfit (IMF) arrays at the GaSb/GaAs interface and strained GaInSb/GaSb multi-quantum wells (MQWs) acting as dislocation filtering layers (DFLs). Cross-sectional transmission electron microscopy (TEM) images revealed that a large part of the dislocations was bonded on the GaAs/GaSb interface due to the IMF arrays, and the four repetitions of the DFL regions can block most of the remaining threading dislocations. Etch pit density (EPD) measurements indicated that the dislocation density in the GaInAsSb material on top of the buffer layer was reduced to the order of 106 /cm2, which was among the lowest for this compound material grown on GaAs. The light emitting diodes (LEDs) based on the GaInAsSb P-N structures on GaAs exhibited strong electro-luminescence (EL) in the 2.0–2.5 µm range. The successful metamorphic growth of GaInAsSb on GaAs with low dislocation densities paved the way for the integration of various GaInAsSb based light emitting devices on the more cost-effective GaAs platform.

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Defects in β-SiC thin films grown on α-SiC substrates

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010010490x ◽

1988 ◽

Vol 46 ◽

pp. 568-569

Author(s):

Karren L. More

Keyword(s):

Thin Films ◽

Semiconductor Device ◽

Lattice Mismatch ◽

Chemical Vapor ◽

Substrate Material ◽

Growth Interface ◽

Si Substrates ◽

Thermal Expansion Coefficients ◽

Device Applications ◽

Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

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Effects of substrate quality and annealing on defect structures at GaAs/Si interfaces

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100126494 ◽

1987 ◽

Vol 45 ◽

pp. 340-341

Author(s):

H. L. Tsai ◽

J. W. Lee

Keyword(s):

Growth Process ◽

Molecular Beam ◽

Substrate Surface ◽

Lattice Misfit ◽

Device Fabrication ◽

Silicon Substrates ◽

Defect Structures ◽

Gaas Film ◽

Substrate Quality ◽

Gaas On Si

Growth of GaAs on Si using epitaxial techniques has been receiving considerable attention for its potential application in device fabrication. However, because of the 4% lattice misfit between GaAs and Si, defect generation at the GaAs/Si interface and its propagation to the top portion of the GaAs film occur during the growth process. The performance of a device fabricated in the GaAs-on-Si film can be degraded because of the presence of these defects. This paper describes a HREM study of the effects of both the substrate surface quality and postannealing on the defect propagation and elimination.The silicon substrates used for this work were 3-4 degrees off [100] orientation. GaAs was grown on the silicon substrate by molecular beam epitaxy (MBE).

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TEM investigation of defect reduction and etch pit formation in GaN

MRS Proceedings ◽

10.1557/proc-798-y5.22 ◽

2003 ◽

Vol 798 ◽

Author(s):

Angelika Vennemann ◽

Jens Dennemarck ◽

Roland Kröger ◽

Tim Böttcher ◽

Detlef Hommel ◽

...

Keyword(s):

Electron Microscopy ◽

Dislocation Density ◽

Line Tension ◽

Threading Dislocations ◽

Dislocation Loops ◽

Etch Pits ◽

Defect Reduction ◽

Transmission Electron ◽

Order Of Magnitude ◽

Edge Dislocations

ABSTRACTGaN samples of this study were chemically wet etched to gain easier access to the dislocation sturcture. The scanning electron microscopy and transmission electron microscopy investigations revealed four different types of etch pits. After brief etching, several dislocations with screw component showed large etch pits, which may be correlated with the core of the screw dislocation. By means of SiNx micromasking the dislocation density could be reduced by more than one order of magnitude. The reduction of threading dislocations in the SiNx region in GaN grown on 〈0001〉 sapphire is due to bending of the threading dislocations into the {0001} plane, such that they form dislocation loops if they meet dislocations with opposite Burgers vectors. Accordingly, the achievable reduction of the dislocation density is limited by the probability that these dislocations interact. Edge dislocations bend more easily on account of their low line tension. This results in a preferential bending and reduction of dislocations with edge character.

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Defect Reduction in GaAs Epilayers on Si Substrates Using Strained Layer Superlattices

MRS Proceedings ◽

10.1557/proc-91-99 ◽

1987 ◽

Vol 91 ◽

Cited By ~ 9

Author(s):

N. El-Masry ◽

N. Hamaguchi ◽

J.C.L. Tarn ◽

N. Karam ◽

T.P. Humphreys ◽

...

Keyword(s):

Thermal Annealing ◽

Rapid Thermal Annealing ◽

Buffer Layers ◽

Threading Dislocations ◽

Defect Reduction ◽

Strained Layer ◽

Si Substrates ◽

Density Of Dislocations ◽

Strained Layer Superlattice ◽

Strained Layer Superlattices

ABSTRACTInxGa11-xAs-GaAsl-yPy strained layer superlattice buffer layers have been used to reduce threading dislocations in GaAs grown on Si substrates. However, for an initially high density of dislocations, the strained layer superlattice is not an effective filtering system. Consequently, the emergence of dislocations from the SLS propagate upwards into the GaAs epilayer. However, by employing thermal annealing or rapid thermal annealing, the number of dislocation impinging on the SLS can be significantly reduced. Indeed, this treatment greatly enhances the efficiency and usefulness of the SLS in reducing the number of threading dislocations.

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Dislocation Nucleation and Growth in MOCVD GaN/AlN Films on Stepped and Step-free 4H-SiC Mesa Substrates

MRS Proceedings ◽

10.1557/proc-1090-z05-24 ◽

2008 ◽

Vol 1090 ◽

Author(s):

Mark E. Twigg ◽

Yoosuf N. Picard ◽

Nabil D. Bassim ◽

Joshua D. Caldwell ◽

Michael A. Mastro ◽

...

Keyword(s):

Dominant Role ◽

High Stress ◽

Chemical Vapor ◽

Misfit Strain ◽

Nucleation And Growth ◽

Dislocation Nucleation ◽

Threading Dislocations ◽

Surface Steps ◽

Half Loop ◽

Edge Dislocations

AbstractUsing transmission electron microscopy, we have analyzed dislocations in AlN nucleation layers and GaN films grown by metallorganic chemical vapor deposition (MOCVD) on the (0001) surface of epitaxially-grown 4H-SiC mesas with and without steps. For 4H-SiC substrates free of SiC surface steps, half-loop nucleation and glide parallel to the AlN/SiC interfacial plane play the dominant role in strain relief, with no mechanism for generating threading dislocations. In contrast, 4H-SiC mesa surfaces with steps give rise to regions of high stress at the heteroepitaxial interface, thereby providing an environment conducive to the nucleation and growth of threading dislocations, which act to accommodate misfit strain by the tilting of threading edge dislocations.

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Wafer-Scale, Highly-Ordered Silicon Nanowires Produced by Step-and-Flash Imprint Lithography and Metal-Assisted Chemical Etching

MRS Proceedings ◽

10.1557/opl.2012.1663 ◽

2012 ◽

Vol 1512 ◽

Author(s):

Jian-Wei Ho ◽

Qixun Wee ◽

Jarrett Dumond ◽

Li Zhang ◽

Keyan Zang ◽

...

Keyword(s):

Aspect Ratio ◽

Cross Sections ◽

Silicon Nanowires ◽

High Aspect Ratio ◽

Chemical Etching ◽

Semiconductor Device ◽

Imprint Lithography ◽

Wafer Level ◽

Conventional Photolithography ◽

Metal Assisted Chemical Etching

ABSTRACTA combinatory approach of Step-and-Flash Imprint Lithography (SFIL) and Metal-Assisted Chemical Etching (MacEtch) was used to generate near perfectly-ordered, high aspect ratio silicon nanowires (SiNWs) on 4" silicon wafers. The ordering and shapes of SiNWs depends only on the SFIL nanoimprinting mould used, thereby enabling arbitary SiNW patterns not possible with nanosphere and interference lithography (IL) to be generated. Very densely packed SiNWs with periodicity finer than that permitted by conventional photolithography can be produced. The height of SiNWs is, in turn, controlled by the etching duration. However, it was found that very high aspect ratio SiNWs tend to be bent during processing. Hexagonal arrays of SiNW with circular and hexagonal cross-sections of dimensions 200nm and less were produced using pillar and pore patterned SFIL moulds. In summary, this approach allows highlyordered SiNWs to be fabricated on a wafer-level basis suitable for semiconductor device manufacturing.

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