Damage Removal of Low Energy Ion Implanted BF2 Layers in Silicon

AbstractRecent results indicate that thermal budgets associated with ion implantation induced end of range damage removal is affected by the presence of a free surface. Low energy BF2 implants (6 keV) were done into both single crystal and Ge preamorphized silicon substrates. Rapid thermal processing was used to study the residual end of range defect structure in the temperature range from 700 to 1000°C. 6 keV, 5E14 cm-2 BF2 implantation resulted in formation of continuous amorphous layers approximately 10 nm deep with a mean B penetration of approximately 7 nm. Conventional TEM analysis found the structures to be completely free of any spanning “hairpin” dislocations or stacking faults associated with the BF2 implant for all the annealing temperatures. For anneals between 700 °C and 900°C end of range damage formation resulted, but the size of the dislocation loops remained small. Annealing at 1000°C, 10 seconds showed no evidence of residual end of range damage. Location of the end of range damage region close to the free surface was found to decrease the thermal budget required for the removal of ion implantation induced radiation damage.

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Ultra-Low Energy Ion Implantation of Si into HfO2 and HfSiO-based Structures for Non Volatile Memory Applications

MRS Proceedings ◽

10.1557/proc-1250-g01-07 ◽

2010 ◽

Vol 1250 ◽

Author(s):

Florence Gloux ◽

Pierre-Eugène Coulon ◽

Jesse Groenen ◽

Sylvie Schamm ◽

Gerard Benassayag ◽

...

Keyword(s):

Ion Implantation ◽

Thin Layers ◽

Low Energy ◽

Electrical Measurements ◽

Thermal Budget ◽

Si Nanocrystals ◽

Non Volatile Memory ◽

Memory Applications ◽

Anomalous Oxidation ◽

Post Implantation

AbstractThe fabrication of Si nanocrystals (NCs) in multilayer structures based on HfO2 and alloys for memory applications is carried out using an innovative method, the ultra-low energy (1 keV) ion implantation followed by a post-implantation annealing. Si+ ions are implanted into SiO2 thin layers deposited on top of thin HfO2-based layers. After annealing at high temperature (1050°C), the implantation leads to the formation of a two dimensional array of Si NCs at a distance from the surface larger than expected, due to an anomalous oxidation of the implanted Si. Nevertheless, the best memory windows are obtained at lower thermal budget, when no nanocrystals are present in the layer. This suggests that electrical measurements should always be correlated to structural characterization in order to understand where charge storage occurs.

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A Comparison of Low Energy BF2 Implantation in Si and Ge Preamorphized Silicon

MRS Proceedings ◽

10.1557/proc-128-611 ◽

1988 ◽

Vol 128 ◽

Cited By ~ 7

Author(s):

Gary A. Ruggles ◽

Shin-Nam Hong ◽

Jimmie J. Wortman ◽

Mehmet Ozturk ◽

Edward R. Myers ◽

...

Keyword(s):

Ion Implantation ◽

Crystalline Silicon ◽

Amorphous Layer ◽

Low Energy ◽

Electrical Activation ◽

Silicon Substrates ◽

Boron Diffusion ◽

Junction Depth ◽

Rapid Thermal Anneal ◽

Boron Segregation

ABSTRACTLow energy (6 keV) BF2 implantation was carried out using single crystal, Ge-preamorphized, and Si-preamorphized silicon substrates. Implanted substrates were rapid thermal annealed at temperatures from 600°C to 1050'C and boron channeling, diffusion, and activation were studied. Ge and Si preamorphization energies were chosen to produce nearly identical amorphous layer depths as determined by TEM micrographs (approximately 40 nm in both cases). Boron segregation to the end-of-range damage region was observed for 6 keV BF2 implantation into crystalline silicon, although none was detected in preamorphized substrates. Junction depths as shallow as 50 nm were obtained. In this ultra-low energy regime for ion implantation, boron diffusion was found to be as important as boron channeling in determining the junction depth, and thus, preamorphization does not result in a significant reduction in junction depth. However, the formation of junctions shallower than 100 rmu appears to require RTA temperatures below 1000°C which can lead to incomplete activation unless the substrate has been preamorphized. In the case of preamorphized samples, Hall measurements revealed that nearly complete electrical activation can be obtained for preamorphized samples after a 10 second rapid thermal anneal at temperatures as low as 600°C.

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Dislocation Related PL of Multi-Step Annealed Cz-Si Samples

Solid State Phenomena ◽

10.4028/www.scientific.net/ssp.108-109.773 ◽

2005 ◽

Vol 108-109 ◽

pp. 773-778 ◽

Cited By ~ 3

Author(s):

E.A. Steinman ◽

A.N. Tereshchenko ◽

V.I. Vdovin ◽

Andrzej Misiuk

Keyword(s):

High Temperature ◽

Low Energy ◽

Interstitial Oxygen ◽

Dislocation Loops ◽

Energy Bands ◽

Tem Analysis ◽

Different Temperatures

The samples of Cz Si were subjected to multi-step annealing at different temperatures. After high temperature consequent steps the dislocation related spectra (DRL) were detected from the samples. The main feature of the DRL spectra was the very narrow low energy bands D1/D2, which are unusual for Cz Si. TEM analysis shown that the only candidates for DRL spectra are dislocation loops, punched out from precipitates. To explain the absence of influence of oxygen it was assumed that the distribution of interstitial oxygen is nonuniform in such samples and has some depletion regions in the vicinity of precipitates.

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4H-SiC Defects Evolution by Thermal Processes

Materials Science Forum ◽

10.4028/www.scientific.net/msf.897.181 ◽

2017 ◽

Vol 897 ◽

pp. 181-184 ◽

Cited By ~ 4

Author(s):

Nicolò Piluso ◽

Maria Ausilia di Stefano ◽

Simona Lorenti ◽

Francesco La Via

Keyword(s):

Ion Implantation ◽

Thermal Process ◽

Defect Density ◽

Annealing Process ◽

Fine Tuning ◽

Thermal Processes ◽

Thermal Budget ◽

Annealing Temperatures ◽

Preliminary Annealing

4H-SiC defects evolution after thermal processes has been evaluated. Different annealing temperatures have been used to decrease the defect density of epitaxial layer (as stacking faults) and recover the damage occurred after ion implantation. The propagation of defects has been detected by Photoluminescence tool and monitored during the thermal processes. The results show that implants do not affect the surface roughness and how a preliminary annealing process, before ion implantation step, can be useful in order to reduce the SFs density. It shown the effect of tuned thermal process. A kind of defect, generated by implant and subsequent annealing, can be removed by an appropriate thermal budget, while others can increase. A fine tuning of thermal process parameters, temperature and timing, is useful to recover the crystallographic quality of the epilayer and increase the yield of the power device.

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Flame Annealing of Ion Implanted Silicon

MRS Proceedings ◽

10.1557/proc-13-361 ◽

1983 ◽

Vol 13 ◽

Cited By ~ 1

Author(s):

J. Narayan ◽

R. T. Young

Keyword(s):

Ion Implantation ◽

Solid Phase ◽

Amorphous Layer ◽

Triangular Grid ◽

Silicon Substrates ◽

Dislocation Loops ◽

Implantation Damage ◽

Hydrogen Flame ◽

Van Der Pauw ◽

Flame Annealing

ABSTRACTWe have investigated flame annealing of ion implantation damage (consisting of amorphous layers and dislocation loops) in (100) and (111) silicon substrates. The temperature of a hydrogen flame was varied from 1050 to 1200°C and the interaction time from 5 to 10 seconds. Detailed TEM results showed that a “defect-free” annealing of amorphous layers by solid-phase-epitaxial growth could be achieved up to a certain concentration. However, dislocation loops in the region below the amorphous layer exhibited coarsening,i.e., the average loop size increased while the number density of loops decreased. Above a critical loop density, which was found to be a function of ion implantation variables and substrate temperature, formations of 90° dislocations (a cross-grid of dislocation in (100) and a triangular grid in (111) specimens) were observed. Electrical (Van der Pauw) measurements indicated nearly a complete electrical activation of dopants with mobility comparable to pulsed laser annealed specimens. The characteristics of p-n junction diodes showed a good diode perfection factor of 1.20–1.25 and low reverse bias currents.

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Dopant Enhanced Grain Growth During Crystallization of Amorphous Silicon Using Rapid Thermal Anealing

MRS Proceedings ◽

10.1557/proc-182-115 ◽

1990 ◽

Vol 182 ◽

Cited By ~ 2

Author(s):

R. Kakkad ◽

S. J. Fonash ◽

P. R. Howell

Keyword(s):

Ion Implantation ◽

Amorphous Silicon ◽

Grain Growth ◽

Thermal Budget ◽

Low Resistivity ◽

Annealing Temperatures ◽

Grain Sizes ◽

Precursor Material ◽

Low Thermal Budget

AbstractPECVD a-Si deposited at 250ºC on 7059 glass was used as precursor material to produce low resistivity large grain doped poly Si. The films doped in the range of 1020−1021 cm-3 with P during growth or by ion implantation wereannealed at 700ºC for times 2 to 5 minutes using RTA. A dopant enhanced grain growth was observed with grain sizes of the order of 3 μm for films of only 2000Å thickness. Resistivity as low as 6x10-4 Ω-cm and mobility as highas 34 cm2 /V-sec. were obtained using this low thermal budget process.These values are comparable to those obtained in the literature using significantly higher annealing temperatures.

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