The Effect of Silicide Formation on the Electrical Properties of Gate Oxides

1992 ◽  
Vol 260 ◽  
Author(s):  
J. P. Gambino ◽  
B. Cunningham ◽  
D. A. Buchanan
Keyword(s):  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Rapid Thermal Anneal ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Current Voltage ◽  
Capacitance Voltage

ABSTRACTCoSi2, or TiSi2 formation on gate polysilicon can degrade the current-voltage and capacitance-voltage characteristics of MOS capacitors. Degradation of the gate oxide breakdown field is much more severe for capacitors with TiSi2 than for those with COSi2 TEM reveals evidence for a reaction at the interface between TiSi2 and SiO2, whereas there is no observable reaction between COSi2 and SiO2- The low breakdown fields for devices with TiSi2 may be due to thinning of the gate oxide by the interfacial reaction or mechanical deformation. A high density of electron traps and a small reduction in the breakdown field is observed when COSi2 contacts the gate, possibly due to a compressive stress in the oxide exerted by the suicide. In addition, an increase in the interface state density at the Si-SiO2 interface is seen for all samples exposed to a rapid thermal anneal (RTA) at 800°C, possibly due to the release of H from dangling bonds.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

Improvements on Electrical Properties of Ultra-Thin Silicon Oxides Grown by Microwave Afterglow Oxygen Plasma

1994 ◽  
Vol 347 ◽  
Author(s):  
P. C. Chen ◽  
J. Y. Lin ◽  
H. L. Hwang
Keyword(s):  
Microwave Plasma ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Breakdown Field ◽  
Silicon Oxides ◽  
Oxide Breakdown ◽  
Thin Silicon ◽  
State Densities ◽  
Plasma Annealing

ABSTRACTFundamental characteristics such as the oxide breakdown fields, oxide charges and interface state density of various ultra-thin silicon oxides (≤ 8 nm) grown by microwave plasma afterglow oxidation at low temperatures (400 °C and 600 °C) were investigated. The effective Oxide charge density of 600 °C as-grown oxide was as low as 6×1010 cm-2. The breakdown fields of the oxides were further enhanced and the interface state densities were reduced by employing fluorination (HF soaked) and low temperature N2O plasma annealing. The breakdown field of the thin oxide grown at 600 °C with 15 min N2O plasma annealing was 12 MV/cm. The reduction of interface state density was about 35% for 600 °C fluorinated oxide. When integrated with poly-gate process, the interface state density was as low as 5×1010 cm-2eV-1.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

Thick Oxide Layers on N and P SiC Wafers by a Depo-Conversion Technique

1999 ◽  
Vol 572 ◽  
Author(s):  
Q. Zhang ◽  
V. Madangarli ◽  
I. Khlebnikov ◽  
S. Soloviev ◽  
T. S. Sudarshan
Keyword(s):  
Electrical Properties ◽  
Effective Charge ◽  
High Frequency ◽  
Breakdown Field ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Oxide Layers ◽  
Oxide Breakdown ◽  
Thermal Oxide ◽  
Capacitance Voltage

ABSTRACTThe electrical properties of thick oxide layers on n and p-type 6H-SiC obtained by a depoconversion technique are presented. High frequency capacitance-voltage measurements on MOS capacitors with a ∼ 3000 Å thick oxide indicates an effective charge density comparable to that of MOS capacitors with thermal oxide. The breakdown field of the depo-converted oxide obtained using a ramp response technique indicates a good quality oxide with average values in excess of 6 MV/cm on p-type SiC and 9 MV/cm on n-type SiC. The oxide breakdown field was observed to decrease with increase in MOS capacitor diameter.

Capacitance-Voltage and Interface State Density Characteristics of GaAs and In0.53Ga0.47As MOS Capacitors Incorporating a PECVD Si3N4 Dielectric

2019 ◽  
Vol 35 (3) ◽  
pp. 415-430 ◽  
Author(s):  
Eamon O'Connor ◽  
Vladimir Djara ◽  
Scott Monaghan ◽  
Paul Hurley ◽  
Karim Cherkaoui
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Capacitance Voltage

scholarly journals Barrier Modification by Methyl Violet Organic Dye Molecules of Ag/P-Inp Structures

2016 ◽  
Vol 2 (3) ◽  
pp. 7 ◽  
Author(s):  
Ömer Güllü
Keyword(s):  
Barrier Height ◽  
Methyl Violet ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Mis Structure ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Mis Diode

This work includes fabrication and electrical characterization of Metal/Interlayer/Semiconductor (MIS) structures with methyl violet organic film on p-InP wafer. Metal(Ag)/ Interlayer (methyl violet =MV)/Semiconductor(p-InP) MIS structure presents a rectifying contact behavior. The values of ideality factor (n) and barrier height (BH) for the Ag/MV/p-InP MIS diode by using the current-voltage (I-V) measurement have been extracted as 1.21 and 0.84 eV, respectively. It was seen that the BH value of 0.84 eV calculated for the Ag/MV/p-InP MIS structure was significantly higher than the value of 0.64 eV of Ag/p-InP control contact. This situation was ascribed to the fact that the MV organic interlayer increased the effective barrier height by influencing the space charge region of inorganic semiconductor. The values of diffusion potential and barrier height for the Ag/MV/p-InP MIS diode by using the capacitance-voltage (C-V) measurement have been extracted as 1.21 V and 0.84 eV, respectively. The interface-state density of the Ag/MV/p-InP structure was seen to change from 2.57×1013 eV-1cm-2 to 2.19×1012 eV-1cm-2.

POST‐METALLIZATION ANNEALING OF ULTRA‐THIN REMOTE PLASMA ENHANCED CVD OXIDES

1996 ◽  
Vol 446 ◽  
Author(s):  
L‐Å Ragnarsson ◽  
P. Lundgren ◽  
D. Landheer
Keyword(s):  
Vapour Deposition ◽  
Chemical Vapour ◽  
Interface State ◽  
State Density ◽  
Silicon Substrates ◽  
Constant Voltage ◽  
Remote Plasma ◽  
Current Voltage ◽  
Voltage Stress ◽  
Capacitance Voltage

AbstractA remote plasma enhanced chemical vapour deposition (RPECVD) process was used to deposit thin silicon dioxides on silicon substrates. The oxide properties were compared with thermal oxides with similar thicknesses (2.5–9 nm) using capacitance‐voltage (C‐V), current‐voltage (I‐V) and constant voltage stress measurements (I‐t). Post‐metallization annealing (PMA) showed different annealing dynamics as compared to the thermal oxides for anneal times below approximately 1000 s (at 260 °C) after which the dynamics were similar. The deposited oxides had a higher initial interface state density (Dit) than the thermal oxides, but after PMA they were found to be of the same quality as the thermal oxides. Positive charging of the deposited oxides during constant voltage stress was the same as for thermal oxides, showing that the stress endurance of the two are similar.

GaP-based MIS Capacitors Using a SiN Gate Dielectric

2003 ◽  
Vol 764 ◽  
Author(s):  
A. Chen ◽  
J. Woodall ◽  
X.W. Wang ◽  
T.P. Ma
Keyword(s):  
Electric Field ◽  
Gallium Phosphide ◽  
Gate Dielectric ◽  
Interface State ◽  
State Density ◽  
Constant Current ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Effective Electric Field ◽  
Mis Capacitors

AbstractGallium Phosphide (GaP) Metal-Insulator-Semiconductor (MIS) capacitors were fabricated with synthesized SiN as the gate dielectric. The interface property and the SiN bulk quality were studied with capacitance-voltage (C-V) measurements and current-voltage (I-V) measurements. The total interface state density of 3×1012 cm-2 and the fixed charge density in SiN of 7×1012cm-2 were estimated from the C-V measurements. The leakage current density was as low as 15nA/cm2 at an effective electric field of 3MV/cm. The effective electric field in SiN at breakdown was as high as 10MV/cm. Constant current stress measurements showed bulk trap density of 2×1011 cm-2 in SiN, which is much lower than that for CVD SiN or SiO2.

Heterojuncion Study of Ga0.92In08as(P+)/GaAs(n) Diodes: Correlation of Electrical and Strucrural Characteristics

1989 ◽  
Vol 160 ◽  
Author(s):  
Y.W. Choi ◽  
C.R. Wie ◽  
K.R. Evans ◽  
C.E. Stutz
Keyword(s):  
Low Frequency ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Trap Level ◽  
Fermi Level Pinning ◽  
Pinning Effect ◽  
Quasi Fermi Level ◽  
Current Voltage ◽  
Capacitance Voltage

AbstractDifferent in-plane mismatch was introduced by varying the Ga 0.92In0.08As(p+) epilayer thickness (h-0.1, 0.25, 0.5 and lum) on GaAs(n)/GaAs(n+) structure. For sample with h-lum, quasi-Fermi level pinning effect was observed in low temperature forward Current-Voltage characteristic due to high density misfit dislocation. From Vint measurement at low frequency limit in C-2 vs Voltage plot, interface state density Nss was obtained. From Capacitance-Voltage measurements at different frequencies, single-level interface state density Ns was estimated using Schokley-Read-Hall statistics. Both Nss and Ns show their linear relation with epilayer in-plane mismatch. Admittance Spectroscopy shows an interface trap level at about Ev + 0.36 eV with the hole capture cross section cp = 2.7×10-15 cm-2 for the h-lum sample, and at Ev + 0.21 eV with cP = 2.4×10-16 cm-2 for the h-0.5um sample.

scholarly journals Barrier Modification by Methyl Violet Organic Dye Molecules of Ag/P-Inp Structures

2016 ◽  
Vol 2 (3) ◽  
pp. 7 ◽  
Author(s):  
Ömer Güllü
Keyword(s):  
Barrier Height ◽  
Methyl Violet ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Mis Structure ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Mis Diode

This work includes fabrication and electrical characterization of Metal/Interlayer/Semiconductor (MIS) structures with methyl violet organic film on p-InP wafer. Metal(Ag)/ Interlayer (methyl violet =MV)/Semiconductor(p-InP) MIS structure presents a rectifying contact behavior. The values of ideality factor (n) and barrier height (BH) for the Ag/MV/p-InP MIS diode by using the current-voltage (I-V) measurement have been extracted as 1.21 and 0.84 eV, respectively. It was seen that the BH value of 0.84 eV calculated for the Ag/MV/p-InP MIS structure was significantly higher than the value of 0.64 eV of Ag/p-InP control contact. This situation was ascribed to the fact that the MV organic interlayer increased the effective barrier height by influencing the space charge region of inorganic semiconductor. The values of diffusion potential and barrier height for the Ag/MV/p-InP MIS diode by using the capacitance-voltage (C-V) measurement have been extracted as 1.21 V and 0.84 eV, respectively. The interface-state density of the Ag/MV/p-InP structure was seen to change from 2.57×1013 eV-1cm-2 to 2.19×1012 eV-1cm-2.

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