Thick Oxide Layers on N and P SiC Wafers by a Depo-Conversion Technique

1999 ◽  
Vol 572 ◽  
Author(s):  
Q. Zhang ◽  
V. Madangarli ◽  
I. Khlebnikov ◽  
S. Soloviev ◽  
T. S. Sudarshan

ABSTRACTThe electrical properties of thick oxide layers on n and p-type 6H-SiC obtained by a depoconversion technique are presented. High frequency capacitance-voltage measurements on MOS capacitors with a ∼ 3000 Å thick oxide indicates an effective charge density comparable to that of MOS capacitors with thermal oxide. The breakdown field of the depo-converted oxide obtained using a ramp response technique indicates a good quality oxide with average values in excess of 6 MV/cm on p-type SiC and 9 MV/cm on n-type SiC. The oxide breakdown field was observed to decrease with increase in MOS capacitor diameter.

2006 ◽  
Vol 527-529 ◽  
pp. 983-986
Author(s):  
Kevin Matocha ◽  
Chris S. Cowen ◽  
Richard Beaupre ◽  
Jesse B. Tucker

4H-SiC MOS capacitors were used to characterize the effect of reactive-ion etching of the SiC surface on the electrical properties of N2O-grown thermal oxides. The oxide breakdown field reduces from 9.5 MV/cm with wet etching to saturate at 9.0 MV/cm with 30% reactive-ion over-etching. Additionally, the conduction-band offset barrier height, φB, progressively decreases from 2.51 eV with wet etching to 2.46 eV with 45% reactive-ion over-etching.


2011 ◽  
Vol 679-680 ◽  
pp. 326-329
Author(s):  
Ioana Pintilie ◽  
Francesco Moscatelli ◽  
Roberta Nipoti ◽  
Antonella Poggi ◽  
Sandro Solmi ◽  
...  

The effect of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface on the capacitance of the MOS capacitors is investigated. The Thermal Dielectric Relaxation Current (TDRC) technique and Capacitance-Voltage (C-V) measurements performed at different temperatures and probe frequencies on an N implanted sample and on a virgin sample were employed for this purpose. There are three types of defects located at or near the interface, Dit, NIToxfast and NIToxslow that can be distinguished. Only Dit and NIToxfast respond to the a.c. small, high frequency signal at temperatures above 150K. The separation of Dit from the NIToxfast states have enabled us to study the influence of the excess of interfacial Nitrogen on each of the mentioned defects. It has been found that the N-implantation process fully suppresses the formation of NIToxfast and partially NIToxslow and Dit. Theoretical C-V characteristics were computed, based on the defect distributions determined by TDRC, and compared with the experimental ones showing a close agreement.


1992 ◽  
Vol 260 ◽  
Author(s):  
J. P. Gambino ◽  
B. Cunningham ◽  
D. A. Buchanan

ABSTRACTCoSi2, or TiSi2 formation on gate polysilicon can degrade the current-voltage and capacitance-voltage characteristics of MOS capacitors. Degradation of the gate oxide breakdown field is much more severe for capacitors with TiSi2 than for those with COSi2 TEM reveals evidence for a reaction at the interface between TiSi2 and SiO2, whereas there is no observable reaction between COSi2 and SiO2- The low breakdown fields for devices with TiSi2 may be due to thinning of the gate oxide by the interfacial reaction or mechanical deformation. A high density of electron traps and a small reduction in the breakdown field is observed when COSi2 contacts the gate, possibly due to a compressive stress in the oxide exerted by the suicide. In addition, an increase in the interface state density at the Si-SiO2 interface is seen for all samples exposed to a rapid thermal anneal (RTA) at 800°C, possibly due to the release of H from dangling bonds.


2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.


2007 ◽  
Vol 556-557 ◽  
pp. 647-650 ◽  
Author(s):  
Jeong Hyun Moon ◽  
Dong Hwan Kim ◽  
Ho Keun Song ◽  
Jeong Hyuk Yim ◽  
Wook Bahng ◽  
...  

We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with ultra thin (5 nm) remote-PECVD SixNy dielectric layers and investigated electrical properties of nitrided SiO2/4H-SiC interface after oxidizing the SixNy in dry oxygen at 1150 °C for 30, 60, 90 min. Improvements of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements in comparison with dry oxide. The improvements of SiC MOS capacitors formed by oxidizing the pre-deposited SixNy have been explained in this paper.


1993 ◽  
Vol 303 ◽  
Author(s):  
Y. Ma ◽  
T. YAsuda ◽  
G. Lucovsky

ABSTRACTSiO2 thin films were deposited by remote PECVD on Si surfaces exposed to species generated in O2/N2 and O2/NH3 plasmas. The surface chemistry was studied by Auger Electron Spectroscopy, AES, and the electrical properties of the SiO2/Si interface by high frequency and quasi-static Capacitance-Voltage, C-V, measurements. The AES results showed that Ccontamination was removed by exposure to both plasma-excited gas mixtures, but that N-atoms were incorporated into the SiO2 film, and Si-N bonds were formed at the SiO2/Si interface. C-V measurements indicated that the Si-N bonding structure, rather than the N-atom concentration, is critical in determining the interface electrical properties. The effects of Rapid Thermal Annealing, RTA, on the electrical properties of these SiO2/Si interfaces were also studied.


2016 ◽  
Vol 858 ◽  
pp. 701-704
Author(s):  
Patrick Fiorenza ◽  
Salvatore di Franco ◽  
Filippo Giannazzo ◽  
Simone Rascunà ◽  
Mario Saggio ◽  
...  

In this work, the combined effect of a shallow phosphorus (P) pre-implantation and of a nitridation annealing in N2O on the properties of the SiO2/4H-SiC interface has been investigated. The peak carrier concentration and depth extension of the electrically active dopants introduced by the nitridation and by the combination of P pre-implantation and nitridation were determined by high resolution scanning capacitance microscopy (SCM). Macroscopic capacitance-voltage (C-V) measurements on metal oxide semiconductor (MOS) capacitors and nanoscale C-V analyses by SCM allowed to quantify the electrical effect of the donors introduced underneath the SiO2/4H-SiC interface. Phosphorous pre-implantation and subsequent high temperature electrical activation has been shown not only to produce an increased doping in the 4H-SiC surface region but also a better homogeneity of surface potential with respect to the use of N2O annealing only.


2010 ◽  
Vol 645-648 ◽  
pp. 689-692 ◽  
Author(s):  
Fernanda Chiarello Stedile ◽  
Silma Alberton Corrêa ◽  
Cláudio Radtke ◽  
Leonardo Miotti ◽  
Israel J.R. Baumvol ◽  
...  

The consequences of thermal treatments in nitric oxide atmospheres on the characteristics of dielectric films / SiC structures was investigated by high-frequency capacitance-voltage measurements, X-ray photoelectron spectroscopy, and X-ray reflectometry techniques. It was observed that nitrogen incorporation in dielectric films / SiC structures leads to the formation of a thinner interfacial layer that contains carbon. This fact was related to the improvement of electrical properties of those structures.


Author(s):  
Xianfeng Chen ◽  
Ming Li ◽  
Qiang Guo ◽  
Kary Chien ◽  
YanBo Gao

Abstract Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.


Sign in / Sign up

Export Citation Format

Share Document