Building in Reliability Through a 100x Reduction in Mobile Ions in a 0.8 μm BiCMOS Process

1996 ◽  
Vol 428 ◽  
Author(s):  
Larry Anderson ◽  
Suketu Parikh ◽  
Samuel Nagalingam
Keyword(s):  
Ammonium Fluoride ◽  
Oxide Thickness ◽  
Hot Electron ◽  
Data Retention ◽  
Voltage Sweep ◽  
Boron Doped ◽  
Gate Oxide Thickness ◽  
Bicmos Process ◽  
Scientists And Engineers ◽  
Mobile Ions

AbstractThe reduction of mobile ions--mainly Na+, but also K+, H+ and Li+, is very critical as our gate oxide thickness and Leff decreases. Hot electron induced hydrogen compensation of boron doped silicon changes the PMOS Leff and NPN BVebo. This paper shows how to reduce Na+ by 100X, through the use of Triangular Voltage Sweep (TVS). This paper is designed to give scientists and engineers a case history where we reduced these levels from 1012 to 1010 mobile ions/cm2 in our 0.8μm BiCMOS process. This was accomplished by adding Ammonium Fluoride mixture dips at appropriate steps. For fast feedback, we can non-destructively measure Na, K, and H within 10 minutes of completing phororesist removal at any of the metallization steps using TVS. In addition to BiCMOS, TVS measure is a power tool in Nonvolatile Memories for predicting in-line data retention, when data retention is associated with charge gain.

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

2007 ◽  
Vol 28 (3) ◽  
pp. 217-219 ◽  
Author(s):  
Meishoku Masahara ◽  
Radu Surdeanu ◽  
Liesbeth Witters ◽  
Gerben Doornbos ◽  
Viet H. Nguyen ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Subthreshold Slope ◽  
Gate Oxide Thickness

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

FABRICATION AND ELECTRICAL PROPERTIES OF Au/PVDF-TrFE/LaZrOx/Si(100) STRUCTURE

2010 ◽  
Vol 24 (22) ◽  
pp. 4203-4208 ◽  
Author(s):  
HUI-SEONG HAN ◽  
GWANG-GEUN LEE ◽  
BYUNG-EUN PARK
Keyword(s):  
Thin Films ◽  
Polyvinylidene Fluoride ◽  
Oxide Thickness ◽  
Voltage Sweep ◽  
Window Width ◽  
Capacitance Voltage ◽  
Coating Method ◽  
Insulator Layers ◽  
Lanthanum Zirconium Oxide ◽  
P Type

Metal-ferroelectric-insulator-semiconductor structure capacitors with a polyvinylidene fluoride trifluoroethylene (75/25) (PVDF-TrFE) ferroelectric and a lanthanum zirconium oxide ( LaZrO x) insulator layers were fabricated on a p-type Si(100) substrate in this work. The thin films were prepared using the spin-coating method. The LaZrO x thin films were crystallized at 750°C for 30 min in an O 2 ambient. Negligible hysteresis was observed from the C–V (capacitance-voltage) characteristic of the LaZrO x/ Si structure. The equivalent oxide thickness (EOT) was about 8.2 nm. Then the PVDF-TrFE film was spin-coated on the LaZrO x/ Si structure. To crystallize the PVDF-TrFE, the structure was annealed at 165°C for 30 min. The memory window width in the C–V curve of the Au/PVDF - TrFE/LaZrO x/ Si structure was about 4 V for a voltage sweep of ±5 V, and the leakage current density was about 10-8 A/cm 2 at 35 kV/cm for a 100-nm-thick film.

Impact Ionization, Degradation, and Breakdown in SiO2

1992 ◽  
Vol 284 ◽  
Author(s):  
D. J. Dimaria ◽  
E. Cartier ◽  
D. Arnold
Keyword(s):  
Silicon Dioxide ◽  
Temperature Dependence ◽  
Impact Ionization ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Bandgap Energy ◽  
Strongly Correlated ◽  
Hot Electron ◽  
Defect Production ◽  
Oxide Degradation

ABSTRACTDestructive breakdown in silicon dioxide is shown to be strongly correlated to the oxide degradation caused by hot-electron-induced defect production and charge trapping ner the interfaces of the films. Two well defined transitions in the chargc-to-breakdown data as a function of field and oxide thickness are shown to coincide with the onset of mechanisms due to trap creation and impact ionization by electrons with energies exceeding 2 and 9 eV (the SiO2 bandgap energy), respectively. The temperature dependence of charge-to-breakdown is also shown to be consistent with that of these two defect-producing mechanisms.

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