Rapid Thermal Annealing and Oxidation of Silicon Wafers with Back-Side Films

1997 ◽  
Vol 470 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Thermal Oxidation ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Temperature Control ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Back Side ◽  
Control Accuracy

ABSTRACTTemperatures for lamp-heated rapid thermal processing of wafers with various back-side films were controlled by a Lucent Technologies pyrometer which uses a/c lamp ripple to compensate for emissivity. Process temperatures for anneals of arsenic and boron implants were inferred from post-anneal sheet resistance, and for rapid thermal oxidation, from oxide thickness. Results imply temperature control accuracy of 12°C to 17°C at 3 standard deviations.

Temperature Monitoring by Ripple Pyrometry in Rapid Thermal Processing

1996 ◽  
Vol 429 ◽  
Author(s):  
Binh Nguyenphu ◽  
Minseok Oh ◽  
Anthony T. Fiory
Keyword(s):  
Temperature Control ◽  
Integrated Circuit ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Back Side ◽  
Integrated Circuit Manufacturing ◽  
Current Trends ◽  
Processing Steps ◽  
Electrical Data

AbstractCurrent trends of silicon integrated circuit manufacturing demand better temperature control in various thermal processing steps. Rapid thermal processing (RTP) has become a key technique because its single wafer process can accommodate the reduced thermal budget requirements arising from shrinking the dimensions of devices and the trend to larger wafers. However, temperature control by conventional infrared pyrometry, which is highly dependent on wafer back side conditions, is insufficiently accurate for upcoming technologies. Lucent Technologies Inc., formerly known as AT&T Microelectronics and AT&T Bell Laboratories, has developed a powerful real-time pyrometry technique using the A/C ripple signal from heating lamps for in-situ temperature measurement. Temperature and electrical data from device wafers have been passively collected by ripple pyrometers in three RTP systems and analyzed. In this paper we report the statistical analysis of ripple temperature and electrical data from device wafers for a typical implant anneal process temperature range of 900 to 1000 °C.

Characteristics of Arsenic Doped Polycrystalline Silicon-Gate Capacitors After Rapid Thermal Processing

1987 ◽  
Vol 106 ◽  
Author(s):  
R. Angelucci ◽  
C. Y. Wong ◽  
J. Y.-C. Sun ◽  
G. Scilla ◽  
P. A. McFarland ◽  
...  
Keyword(s):  
Work Function ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Polycrystalline Silicon ◽  
Rapid Thermal Processing ◽  
Interface States ◽  
Fixed Charges ◽  
Polysilicon Gate

ABSTRACTThe feasibility and advantages of using rapid thermal annealing to achieve a proper n+ polysilicon work function are demonstrated. Our data shows that RTA can be used to activate arsenic in the polysilicon gate after a regular furnace anneal or to diffuse and activate arsenic without any prior furnace anneal. Interface states and fixed charges due to RTA can be annealed out at 500°C for 30 min in forming gas. New insights into the diffusion, segregation, and activation of As in polysilicon during furnace and/or rapid thermal annealing have been obtained.

Characterisation of Low Energy Boron Implantation and Fast Ramp-Up Rapid Thermal Annealing

1998 ◽  
Vol 525 ◽  
Author(s):  
E. J. H. Collart ◽  
G. de Cock ◽  
A. J. Murrell ◽  
M. A. Foad
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Low Energy ◽  
Electrical Activation ◽  
Junction Depth ◽  
Boron Implantation

ABSTRACTThe effects of ramp-up rate during rapid thermal processing of ultra-shallow boron implants have been investigated. Ramp-up rates were varied between 25 °C and 200 °C for two types of anneals: soak anneals and spike anneals. It was found that the ramp-up rate had very little influence on junction depth or electrical activation for both types of anneals. Spike anneals did produce shallower profiles than soak anneal for a comparable electrical activation and may be an option for future processes.

Characterization of Doped Si-TiSi2 Bilayers Formed by Ion Beam Mixing and Rapid Thermal Annealing

1985 ◽  
Vol 45 ◽  
Author(s):  
K. Maex ◽  
R.F. de Keersmaecker ◽  
P.F.A. Alkemade
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Ion Beam ◽  
Rapid Thermal Processing ◽  
Ion Beam Mixing ◽  
Simultaneous Formation ◽  
Impurity Redistribution

ABSTRACTThe use of rapid thermal processing is reported for simultaneous formation of TiSi2 from Ti deposited layers and activation of As or Sb implanted profiles in Si. Properties of the silicide and the doped Si are reported with emphasis on impurity redistribution and defect removal.

Rapid Thermal Processing of Thin Film Electroluminescent Display Materials

1988 ◽  
Vol 100 ◽  
Author(s):  
D. M. Kim ◽  
F. Qian ◽  
R. Solanki ◽  
R. T. Tuenge ◽  
C. N. King
Keyword(s):  
Thin Film ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Annealing Temperature ◽  
Rapid Thermal Processing ◽  
Processing Conditions ◽  
Furnace Annealing ◽  
Fatigue Effect

ABSTRACTRapid thermal annealing of the electroluminescent phosphors ZnS:Mn, SrS:CeF3 and ZnS:SmCl3 has been examined as a function of annealing temperature (500–750°C) and time of exposure (10–120 sec.). The resulting brightness and efficiency of luminescence are correlated with the different processing conditions used. The results indicate that the brightness can be significantly improved from the value obtained with furnace annealing without causing film delamination, blistering or fatigue effect.

Effect of a Ti-capped and Ti-mediated Layer on Co Silicide Formation

2002 ◽  
Vol 716 ◽  
Author(s):  
G.Z. Pan ◽  
E.W. Chang ◽  
Y. Rahmat-Samii
Keyword(s):  
Electron Diffraction ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Diffusion Barrier ◽  
Silicide Formation ◽  
Plan View ◽  
Processing Window

AbstractWe comparatively studied the formation of ultra thin Co silicides, Co2Si, CoSi and CoSi2, with/without a Ti-capped and Ti-mediated layer by using rapid thermal annealing in a N2 ambient. Four-point-probe sheet resistance measurements and plan-view electron diffraction were used to characterize the silicides as well as the epitaxial characteristics of CoSi2 with Si. We found that the formation of the Co silicides and their existing duration are strongly influenced by the presence of a Ti-capped and Ti-mediated layer. A Ti-capped layer promotes significantly CoSi formation but suppresses Co2Si, and delays CoSi2, which advantageously increases the silicidation-processing window. A Ti-mediated layer acting as a diffusion barrier to the supply of Co suppresses the formation of both Co2Si and CoSi but energetically favors directly forming CoSi2. Plan-view electron diffraction studies indicated that both a Ti-capped and Ti-mediated layer could be used to form ultra thin epitaxial CoSi2 silicide.

Rapid Thermal Annealing of Ni/Al/Si and Ni/Si Systems

1986 ◽  
Vol 74 ◽  
Author(s):  
A. Katz ◽  
Y. KOMEM
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Reference System ◽  
Diffusion Processes ◽  
Eutectic Temperature ◽  
Melting Process ◽  
Polycrystalline Layer ◽  
Smooth Interface ◽  
And Diffusion

AbstractThe effect of Rapid Thermal Annealing on phase formation and diffusion processes in the Ni(30 nm) /Al(10 nm)/Si system was studied and coxpared to a Ni(30 nm)/Si reference system. Heat treatments were carried out at temperatures between 400°C and 900°C for 2 seconds.The results obtained by means of TEM, AES and XRD indicated that the Ni/Al/Si system underwent a local melting in the intermediate Al layer at the Al/Si eutectic temperature (577°C). This reaction, due to the rapid melting process, resulted in formation of a unique layered-structure composed of a columnar polycrystalline layer (60 nm thick) of Ni2Si and NiSi adjacent to the Si substrate with relatively smooth interface and an outer layer of two separate polycrystalline films (both about 10 m thick) of Al3Ni (inside) and Ni(Al0.5Si0.5 ) (outside). Under the same rapid thermal processing conditions the Ni/Si reference system underwent a solid state reaction which resulted in the formation of a polycrystalline layer (60 nm thick) composed of Ni2Si and NiSi as well as NiSi2.

Formation and Morphology Evolution of Nickel Germanides on Ge (100) under Rapid Thermal Annealing

2004 ◽  
Vol 810 ◽  
Author(s):  
K.Y. Lee ◽  
S.L. Liew ◽  
S.J. Chua ◽  
D.Z. Chi ◽  
H.P. Sun ◽  
...  
Keyword(s):  
Grain Growth ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Microstructure Evolution ◽  
Interfacial Microstructure ◽  
Morphology Evolution ◽  
Smooth Interface ◽  
Substrate Side ◽  
Nickel Germanides

ABSTRACTPhase formation and interfacial microstructure evolution of nickel germanides formed by rapid thermal annealing in a 15-nm Ni/Ge (100) system have been studied. Coexistence of a NiGe layer and Ni-rich germanide particles was detected at 250°C. Highly textured NiGe film with a smooth interface with Ge was observed. Annealing at higher temperatures resulted in grain growth and severe grooving of the NiGe film at the substrate side, followed by serious agglomeration above 500°C. Fairly low sheet resistance was achieved in 250-500°C where the NiGe film continuity was uninterrupted.

Optimization of Process Parameter and Temperature Uniformity On Wafers For Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
Andreas Tillmann
Keyword(s):  
Standard Deviation ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Simulation Software ◽  
Process Parameter ◽  
Parameter Distribution ◽  
Temperature Uniformity ◽  
New Strategy ◽  
The Impact

AbstractA new strategy based algorithm to optimize process parameter uniformity (e.g.sheet resistance, oxide thickness) and temperature uniformity on wafers in a commercially available Rapid Thermal Processing (RTP) system with independent lamp control is described. The computational algorithm uses an effective strategy to minimize the standard deviation of the considered parameter distribution. It is based on simulation software which is able to calculate the temperature and resulting parameter distribution on the wafer for a given lamp correction table. A cyclical variation of the correction values of all lamps is done while minimizing the standard deviation of the considered process parameter. After the input of experimentally obtained wafer maps the optimization can be done within a few minutes. This technique is an effective tool for the process engineer to use to quickly optimize the homogeneity of the RTP tool for particular process requirements. The methodology will be shown on the basis of three typical RTP applications (Rapid Thermal Oxidation, Titanium Silicidation and Implant Annealing). The impact of variations of correction values for single lamps on the resulting process uniformity for different applications will be discussed.

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