High Quality Germanium Photodiodes on Silicon Substrates Using an Intermediate Chemical Mechanical Polishing Step

1997 ◽  
Vol 486 ◽  
Author(s):  
Srikanth B. Samavedam ◽  
Matthew T. Currie ◽  
Thomas A. Langdo ◽  
Steve M. Ting ◽  
Eugene A. Fitzgerald
Keyword(s):  
Dislocation Density ◽  
Chemical Mechanical Polishing ◽  
Mechanical Polishing ◽  
Quantum Yields ◽  
Threading Dislocation ◽  
Thermal Mismatch ◽  
High Quality ◽  
Si Substrates ◽  
Threading Dislocation Density ◽  
Graded Layers

AbstractGermanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz frequencies in the 1–1.6 μm wavelength regime. The compatibility of SiGe alloys with Si substrates makes Ge a natural choice for photodetectors in Si-based optoelectronics applications. The large lattice mismatch (≈4%) between Si and Ge, however, leads to the formation of a high density of misfit and associated threading dislocations when uniform Ge layers are grown on Si substrates. High quality Ge layers were grown on relaxed graded SiGe/Si layers by ultra-high vacuum chemical vapor deposition (UHVCVD). Typically, as the Ge concentration in the graded layers increases, strain fields from underlying misfit dislocations result in increased surface roughness and the formation of dislocation pile-ups. The generation of pile-ups increases the threading dislocation density in the relaxed layers. In this study the pileup formation was minimized by growing on miscut (001) substrates employing a chemical mechanical polishing (CMP) step within the epitaxial structure. Other problems such as the thermal mismatch between Si and Ge, results in unwanted residual tensile stresses and surface microcracks when the substrates are cooled from the growth temperature. Compressive strain has been incorporated into the graded layers to overcome the thermal mismatch problem, resulting in crack-free relaxed cubic Ge on Si at room temperature. The overall result of the CMP step and the growth modifications have eliminated dislocation pile-ups, decreased gas-phase nucleation of particles, and eliminated the increase in threading dislocation density that occurs when grading to Ge concentrations greater than 70% Ge. The threading dislocation density in the Ge layers determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range of 2 × 106/cm2. Ge p-n diodes were fabricated to assess the electronic quality and prove the feasibility of high quality photodetectors on Si substrates.

Mid-10 cm−2 threading dislocation density in optimized high-Ge content relaxed graded SiGe on Si for III-V solar on Si

2004 ◽  
Vol 836 ◽  
Author(s):  
David M. Isaacson ◽  
Carl L. Dohrman ◽  
Arthur J. Pitera ◽  
Saurabh Gupta ◽  
Eugene A. Fitzgerald
Keyword(s):  
Solar Cells ◽  
Dislocation Density ◽  
Minority Carrier ◽  
Dislocation Nucleation ◽  
Threading Dislocation ◽  
High Quality ◽  
Significant Development ◽  
Threading Dislocation Density ◽  
Free Growth

ABSTRACTWe present a framework for obtaining high quality relaxed graded SiGe buffers on Si for III-V integration. By avoiding dislocation nucleation in Si1−xGex layers of x>0.96, we have achieved a relaxed Si0.04Ge0.96 platform on Si(001) offcut 2° that has a threading dislocation density of 7.4×105 cm−2. This 2° offcut orientation was determined to be the minimum necessary for APB-free growth of GaAs. Furthermore, we found that we could compositionally grade the Ge content in the high-Ge portion of the buffer at up to 17 %Ge μm−1 with no penalty to the dislocation density. The reduction in both threading dislocation density and buffer thickness exhibited by our method is an especially significant development for relatively thick minority-carrier devices which use III-V materials such as multi-junction solar cells.

The Influence of Substrate Patterning on Threading Dislocation Density and Residual Stress in GaAs/Si Heteroepitaxial Layers.

1990 ◽  
Vol 198 ◽  
Author(s):  
Hyunchul Sohn ◽  
Eicke R. Weber ◽  
Jay Tu ◽  
Henry P. Lee ◽  
Shy Wang
Keyword(s):  
Residual Stress ◽  
Dislocation Density ◽  
Threading Dislocation ◽  
Etch Pits ◽  
Cross Sectional ◽  
Strained Layers ◽  
Si Substrates ◽  
Growth Area ◽  
Threading Dislocation Density ◽  
Influence Of Substrate

ABSTRACTThe growth of GaAs films by MBE on mesa-type patterned Si substrates has been investigated. Mesa widths were varied from 10 µm to 200 µm and were prepared using chemical etching with Si3N4 masks and reactive ion etching. The residual stress in the epitaxial layer was estimated using low temperature (7K) photoluminescence and the defect distribution was studied by cross sectional TEM, dislocation densities were in addition determined by etch pits. The residual stress and the dislocation density decreased monotonically with the reduction of growth area. By the incorporation of strained layers with the reduction of growth area, the etch pit density in GaAs layers on mesas was reduced further.

Engineering Dislocation Dynamics in Inx(AlyGa1−y)1−xP Graded Buffers Grown on Gap by Movpe

1998 ◽  
Vol 510 ◽  
Author(s):  
A.Y. Kim ◽  
E.A. Fitzgerald
Keyword(s):  
Surface Roughness ◽  
Dislocation Density ◽  
Growth Conditions ◽  
Dislocation Nucleation ◽  
Dislocation Dynamics ◽  
Threading Dislocation ◽  
High Quality ◽  
Movpe Growth ◽  
Threading Dislocation Density ◽  
Buffer Design

AbstractTo engineer high-quality Inx(AlyGa1−y)1−x P/Ga1−xP graded buffers, we have explored the effects of graded buffer design and MOVPE growth conditions on material quality. We demonstrate that surface roughness causes threading dislocation density (TDD) to increase with continued grading: dislocations and roughness interact in a recursive, escalating cycle to form pileups that cause increasing roughness and dislocation nucleation. Experiments show that V/III ratio, temperature, and grading rate can be used to control dislocation dynamics and surface roughness in InxGa1−xP graded buffers. Control of these parameters individually has resulted in x = 0.34 graded buffers with TDD = 5 × 106 cm−2and roughness = 15 nm and a simple optimization has resulted in TDD = 3 × 106 cm −2and roughness = 10 un. Our most recent work has focused on more sophisticated optimization and the incorporation of aluminum for x > 0.20 to keep the graded buffer completely transparent above 545 nm. Given our results, we expect to achieve transparent, device-quality Inx(AlyGa1−y)1−x P/GaP graded buffers with TDD < 106 cm−2

The Reduction of The Defect Density in CdTe Buffer Layers for The Growth of HgCdTe Infrared Photodiodes on Si (211) Substrates

1997 ◽  
Vol 484 ◽  
Author(s):  
H.-Y. Wei ◽  
L. Salamanca-Riba ◽  
N. K. Dhar
Keyword(s):  
Dislocation Density ◽  
Defect Density ◽  
Three Dimensional ◽  
Buffer Layers ◽  
Threading Dislocation ◽  
Si Substrates ◽  
Migration Enhanced Epitaxy ◽  
Threading Dislocation Density ◽  
Order Of Magnitude ◽  
Cdte Buffer

CdTe epilayers were grown by molecular beam epitaxy on As-passivated nominal (211) Si substrates using thin interfacial ZnTe layers. By using thin recrystallized (initially amorphous) ZnTe buffei layers, we utilized migration enhanced epitaxy (MEE) in the ZnTe layer and overcome the tendency toward three dimensional nucleation. The threading dislocation densities in 8–9 tm thick CdTe films deposited on the recrystallized amorphous ZnTe films were in the range of 2 to 5 × 105 cm−2. In addition to the reduction of threading dislocation density, the interface between the ZnTe layers and the Si substrate is much smoother and the microtwin density is an order of magnitude lower than in regular MEE growth. In order to understand the initial nucleation mechanism of the ZnTe on the As precursor Si surface, we also grew ZnTe epilayers on Te precursor treated Si substrates. The growth mode, microtwin density, and threading dislocation density are compared for films grown on Si substrates with different surface precursors and grown by different growth methods.

The Reduction of The Defect Density in CdTe Buffer Layers for The Growth of HgCdTe Infrared Photodiodes on Si (211) Substrates

1997 ◽  
Vol 487 ◽  
Author(s):  
H.-Y. Wei ◽  
L. Salamanca-Riba ◽  
N. K. Dhar
Keyword(s):  
Dislocation Density ◽  
Defect Density ◽  
Three Dimensional ◽  
Buffer Layers ◽  
Threading Dislocation ◽  
Si Substrates ◽  
Migration Enhanced Epitaxy ◽  
Threading Dislocation Density ◽  
Order Of Magnitude ◽  
Cdte Buffer

CdTe epilayers were grown by molecular beam epitaxy on As-passivated nominal (211) Si substrates using thin interfacial ZnTe layers. By using thin recrystallized (initially amorphous) ZnTe buffer layers, we utilized migration enhanced epitaxy (MEE) in the ZnTe layer and overcome the tendency toward three dimensional nucleation. The threading dislocation densities in 8–9 μm thick CdTe films deposited on the recrystallized amorphous ZnTe films were in the range of 2 to 5 × 105 cm−2. In addition to the reduction of threading dislocation density, the interface between the ZnTe layers and the Si substrate is much smoother and the microtwin density is an order of magnitude lower than in regular MEE growth. In order to understand the initial nucleation mechanism of the ZnTe on the As precursor Si surface, we also grew ZnTe epilayers on Te precursor treated Si substrates. The growth mode, microtwin density, and threading dislocation density are compared for films grown on Si substrates with different surface precursors and grown by different growth methods.

Threading Dislocation Density Reduction in GaAs on Si Substrates

1988 ◽  
Vol 27 (Part 2, No. 12) ◽  
pp. L2271-L2273 ◽  
Author(s):  
Takashi Nishioka ◽  
Yoshio Itoh ◽  
Mitsuru Sugo ◽  
Akio Yamamoto ◽  
Masfumi Yamaguchi
Keyword(s):  
Dislocation Density ◽  
Threading Dislocation ◽  
Si Substrates ◽  
Gaas On Si ◽  
Density Reduction ◽  
Threading Dislocation Density

Role of Dislocation Interactions in Decreasing Mobile Threading Dislocation Density and Limiting Strain Relaxation in Si1-xGex Heteroepitaxial Films

1994 ◽  
Vol 356 ◽  
Author(s):  
Veronique T Gillard ◽  
William D Nix
Keyword(s):  
Dislocation Density ◽  
Late Stage ◽  
Strain Relaxation ◽  
Threading Dislocation ◽  
Misfit Dislocations ◽  
Si Substrates ◽  
Good Account ◽  
Dislocation Interactions ◽  
Threading Dislocation Density ◽  
Residual Strains

AbstractIn situ substrate curvature measurements obtained during isothermal annealing of Si1-xGex films grown on (001) Si substrates allow determination of the evolution of strain versus time in these films. By coupling the strain relaxation measurements with previous measurements of dislocation velocities in this system, the mobile threading dislocation density and its evolution in the course of strain relaxation can be determined. The results indicate that in the late stage of strain relaxation, the mobile threading dislocation density decreases significantly. Results obtained with samples of two different sizes show that this decrease in mobile dislocation density is not primarily associated with dislocations running out at the edges of the film but with dislocation interactions impeding their further motion. Furthermore, for films thinner than 500 nm the residual strains after annealing are significantly higher than the values predicted by the equilibrium theory of misfit dislocations. The measured residual strains are compared with predictions based on Freund’s treatment of the blocking of a moving threading segment by an orthogonal misfit dislocation in its path. We find that the blocking criterion gives a very good account of the residual strain in Si1-xGex films and that blocking of threading dislocations by other misfit dislocations appears to play an important role in the late stage of strain relaxation.

Defect Reduction in GaAs Grown on Si by Using Saw-Tooth-Patterned Substrates

1992 ◽  
Vol 281 ◽  
Author(s):  
Jane G. Zhu ◽  
M. M. Al-Jassim ◽  
N. H. Karam ◽  
K. M. Jones
Keyword(s):  
Dislocation Density ◽  
Chemical Vapor ◽  
Growth Front ◽  
Organic Chemical ◽  
Threading Dislocation ◽  
Defect Reduction ◽  
Dislocation Configuration ◽  
Si Substrates ◽  
Transmission Electron ◽  
Threading Dislocation Density

ABSTRACTEpitaxial GaAs layers have been grown on saw-tooth-patterned (STP) Si substrates by metal-organic chemical vapor deposition and analyzed by transmission electron microscopy. The utilization of this special interface feature is effective in suppressing the formation of antiphase boundaries and reducing the threading dislocation density. The growth of GaAs has been studied with the epilayer thicknesses ranging from several hundred angstroms to several microns. Very flat growth front on (100) plane above the STP region is observed. The dislocation density decreases very rapidly in the area farther away from the interface. The dislocation configuration at this STP interface is very different from that at the extensively studied two-dimensional planar interface.

High-Speed Growth of 4H-SiC Single Crystal Using Si-Cr Based Melt

2013 ◽  
Vol 740-742 ◽  
pp. 73-76 ◽  
Author(s):  
Motohisa Kado ◽  
Hironori Daikoku ◽  
Hidemitsu Sakamoto ◽  
Hiroshi Suzuki ◽  
Takeshi Bessho ◽  
...  
Keyword(s):  
Dislocation Density ◽  
Single Crystal ◽  
High Speed ◽  
High Rate ◽  
Threading Dislocation ◽  
High Quality ◽  
X Ray ◽  
Interface Kinetics ◽  
Threading Dislocation Density ◽  
Rate Limiting

In this study, we have investigated the rate-limiting process of 4H-SiC solution growth using Si-Cr based melt, and have tried high-speed growth. It is revealed that the rate-limiting process of SiC growth under our experimental condition is interface kinetics, which can be controlled by such factors as temperature and supersaturation of carbon. By enhancing the interface kinetics, SiC crystal has been grown at a high rate of 2 mm/h. The FWHM values of X-ray rocking curves and threading dislocation density of the grown crystals are almost the same as those of seed crystal. Possibility of high-speed and high-quality growth of 4H-SiC has been indicated.

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