High-Speed Growth of 4H-SiC Single Crystal Using Si-Cr Based Melt

2013 ◽  
Vol 740-742 ◽  
pp. 73-76 ◽  
Author(s):  
Motohisa Kado ◽  
Hironori Daikoku ◽  
Hidemitsu Sakamoto ◽  
Hiroshi Suzuki ◽  
Takeshi Bessho ◽  
...  

In this study, we have investigated the rate-limiting process of 4H-SiC solution growth using Si-Cr based melt, and have tried high-speed growth. It is revealed that the rate-limiting process of SiC growth under our experimental condition is interface kinetics, which can be controlled by such factors as temperature and supersaturation of carbon. By enhancing the interface kinetics, SiC crystal has been grown at a high rate of 2 mm/h. The FWHM values of X-ray rocking curves and threading dislocation density of the grown crystals are almost the same as those of seed crystal. Possibility of high-speed and high-quality growth of 4H-SiC has been indicated.

1998 ◽  
Vol 535 ◽  
Author(s):  
P. J. Taylor ◽  
W.A. Jesser ◽  
G. Simonis ◽  
W. Chang ◽  
M. Lara-Taysing ◽  
...  

AbstractThe growth of reduced dislocation density GaAs/Si is performed by a novel two-step technique where the first epitaxy step takes place at 75° C and the second is performed at 580° C. The initial deposition is single crystal, continuous, and planar such that there is no contribution to the dislocation density from Volmer-Weber island coalescence and no trapping of dislocations in pinholes. Using this new growth technique, a reduced dislocation density the order of 106/cm2 was obtained. The improved crystallinity is indicated by the more narrow x-ray full-width-at-half-maximum (FWHM) value of 110 arcseconds. GaAs p-i-n diodes were grown on the reduced dislocation density GaAs/Si and it was found that the resistivity of the intrinsic region for the heteroepitaxial diodes was similar to homoepitaxial ones for small mesa sizes.


2017 ◽  
Vol 26 (12) ◽  
pp. 127309 ◽  
Author(s):  
Yuan-Hao Miao ◽  
Hui-Yong Hu ◽  
Xin Li ◽  
Jian-Jun Song ◽  
Rong-Xi Xuan ◽  
...  

2004 ◽  
Vol 836 ◽  
Author(s):  
David M. Isaacson ◽  
Carl L. Dohrman ◽  
Arthur J. Pitera ◽  
Saurabh Gupta ◽  
Eugene A. Fitzgerald

ABSTRACTWe present a framework for obtaining high quality relaxed graded SiGe buffers on Si for III-V integration. By avoiding dislocation nucleation in Si1−xGex layers of x>0.96, we have achieved a relaxed Si0.04Ge0.96 platform on Si(001) offcut 2° that has a threading dislocation density of 7.4×105 cm−2. This 2° offcut orientation was determined to be the minimum necessary for APB-free growth of GaAs. Furthermore, we found that we could compositionally grade the Ge content in the high-Ge portion of the buffer at up to 17 %Ge μm−1 with no penalty to the dislocation density. The reduction in both threading dislocation density and buffer thickness exhibited by our method is an especially significant development for relatively thick minority-carrier devices which use III-V materials such as multi-junction solar cells.


1998 ◽  
Vol 510 ◽  
Author(s):  
A.Y. Kim ◽  
E.A. Fitzgerald

AbstractTo engineer high-quality Inx(AlyGa1−y)1−x P/Ga1−xP graded buffers, we have explored the effects of graded buffer design and MOVPE growth conditions on material quality. We demonstrate that surface roughness causes threading dislocation density (TDD) to increase with continued grading: dislocations and roughness interact in a recursive, escalating cycle to form pileups that cause increasing roughness and dislocation nucleation. Experiments show that V/III ratio, temperature, and grading rate can be used to control dislocation dynamics and surface roughness in InxGa1−xP graded buffers. Control of these parameters individually has resulted in x = 0.34 graded buffers with TDD = 5 × 106 cm−2and roughness = 15 nm and a simple optimization has resulted in TDD = 3 × 106 cm −2and roughness = 10 un. Our most recent work has focused on more sophisticated optimization and the incorporation of aluminum for x > 0.20 to keep the graded buffer completely transparent above 545 nm. Given our results, we expect to achieve transparent, device-quality Inx(AlyGa1−y)1−x P/GaP graded buffers with TDD < 106 cm−2


2020 ◽  
Vol 1004 ◽  
pp. 63-68
Author(s):  
Rafael Dalmau ◽  
Jeffrey Britt ◽  
Hao Yang Fang ◽  
Balaji Raghothamachar ◽  
Michael Dudley ◽  
...  

Large diameter aluminum nitride (AlN) substrates, up to 50 mm, were manufactured from single crystal boules grown by physical vapor transport (PVT). Synchrotron-based x-ray topography (XRT) was used to characterize the density, distribution, and type of dislocations. White beam topography images acquired in transmission geometry were used to analyze basal plane dislocations (BPDs) and low angle grain boundaries (LAGBs), while monochromatic beam, grazing incidence images were used to analyze threading dislocations. Boule diameter expansion, without the introduction of LAGBs around the periphery, was shown. A 48 mm substrate with a uniform threading dislocation density below 7.0 x 102 cm-2 and a BPD of 0 cm-2, the lowest dislocation densities reported to date for an AlN single crystal this size, was demonstrated.


MRS Advances ◽  
2018 ◽  
Vol 3 (18) ◽  
pp. 931-936
Author(s):  
F. B. Abas ◽  
R. Fujita ◽  
S. Mouri ◽  
T. Araki ◽  
Y. Nanishi

ABSTRACTThe objective of this study was to investigate the relationship between the thickness of N radical irradiated InN template with crystallographic quality and electrical properties of InN film grown with the previously proposed method, in situ surface modification by radical beam irradiation. In this study, three InN samples were grown with this method on different thickness of irradiated templates. The crystallographic quality of InN films was analyzed by X-ray diffraction and the electrical properties were studied by Hall effect measurement. InN grown on 100 nm thick irradiated template shows lower full-width at half-maximum of X-ray rocking curves and lower carrier concentration compared to InN grown on 200 nm and 450 nm thick irradiated templates. Transmission electron microscopy revealed that threading dislocation density in the InN film decreased by an order of magnitude to ∼4.6×109cm-2. These results suggest that this method is possible for reduction of threading dislocation density in InN and the thickness of irradiated template should be minimized for higher crystallographic quality and electrical properties of the entire InN film.


1997 ◽  
Vol 486 ◽  
Author(s):  
Srikanth B. Samavedam ◽  
Matthew T. Currie ◽  
Thomas A. Langdo ◽  
Steve M. Ting ◽  
Eugene A. Fitzgerald

AbstractGermanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz frequencies in the 1–1.6 μm wavelength regime. The compatibility of SiGe alloys with Si substrates makes Ge a natural choice for photodetectors in Si-based optoelectronics applications. The large lattice mismatch (≈4%) between Si and Ge, however, leads to the formation of a high density of misfit and associated threading dislocations when uniform Ge layers are grown on Si substrates. High quality Ge layers were grown on relaxed graded SiGe/Si layers by ultra-high vacuum chemical vapor deposition (UHVCVD). Typically, as the Ge concentration in the graded layers increases, strain fields from underlying misfit dislocations result in increased surface roughness and the formation of dislocation pile-ups. The generation of pile-ups increases the threading dislocation density in the relaxed layers. In this study the pileup formation was minimized by growing on miscut (001) substrates employing a chemical mechanical polishing (CMP) step within the epitaxial structure. Other problems such as the thermal mismatch between Si and Ge, results in unwanted residual tensile stresses and surface microcracks when the substrates are cooled from the growth temperature. Compressive strain has been incorporated into the graded layers to overcome the thermal mismatch problem, resulting in crack-free relaxed cubic Ge on Si at room temperature. The overall result of the CMP step and the growth modifications have eliminated dislocation pile-ups, decreased gas-phase nucleation of particles, and eliminated the increase in threading dislocation density that occurs when grading to Ge concentrations greater than 70% Ge. The threading dislocation density in the Ge layers determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range of 2 × 106/cm2. Ge p-n diodes were fabricated to assess the electronic quality and prove the feasibility of high quality photodetectors on Si substrates.


1994 ◽  
Vol 356 ◽  
Author(s):  
C. C. R. Watson ◽  
K. Durose ◽  
E. O’Keefe ◽  
J. M. Hudson ◽  
B. K. Tanner

Epilayers of LPE Cdo.24Hgo.76Te grown on (111)B CdTe and Cdi-xZnxTe substrates have been examined by defect etching and triple axis x-ray diffraction. Defect etching of bevelled layers has shown the threading dislocation density to fall with increasing distance from the heterointerface, for distances <6μm. In thicker regions however a constant ‘background’ dislocation density is observed. Background dislocation densities of ∼ 3 x 105cm-2 and 9 x 104cm-2 have been measured for layers grown on CdTe and Cdo.96Zn0.04Te respectively, this is compared with a substrate dislocation density of ∼ 3 x 104cm-2 measured in both types of substrates. The increase in the dislocation density within the epilayers compared with the corresponding substrate is discussed. An explanation is also given for the displacement of the peak dislocation density, from the interface to within the layer, observed in the Cd0.76Hg0.24Te / Cd0.96Zn0.04Te system.


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