Silicon Carbide: Progress in Crystal Growth

1987 ◽  
Vol 97 ◽  
Author(s):  
J. Anthony Powell
Keyword(s):  
Silicon Carbide ◽  
Crystal Growth ◽  
High Temperature ◽  
Epitaxial Growth ◽  
Recent Progress ◽  
Single Crystal Silicon ◽  
Silicon Substrates ◽  
Large Area ◽  
High Quality ◽  
Crystal Silicon

ABSTRACTSilicon carbide (SiC), with a favorable combination of semiconducting and refractory properties, has long been a candidate for high temperature semiconductor applications. Research on processes for producing the needed large-area high quality single crystals has proceeded sporadically for many years. Two characteristics of SiC have aggravated the problem of its crystal growth. First, it cannot be melted at any reasonable pressure, and second, it forms many different crystalline structures, called polytypes. Recent progress in the development of two crystal growth processes will be described. These processes are the modified Lely process for the growth of the alpha polytypes (e.g. 6H SiC), and a process for the epitaxial growth of the beta polytype (i.e. 3C or cubic SiC) on single crystal silicon substrates. A discussion of the semiconducting qualities of crystals grown by various techniques will also be included.

Silicon Carbide Die Attach Scheme for 500°C Operation

2000 ◽  
Vol 622 ◽  
Author(s):  
Liang-Yu Chen ◽  
Gary W. Hunter ◽  
Philip G. Neudeck
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Electrical Resistance ◽  
Room Temperature ◽  
Semiconductor Devices ◽  
Single Crystal Silicon ◽  
Film Material ◽  
Crystal Silicon ◽  
Pure Alumina ◽  
Die Attach

ABSTRACTSingle crystal silicon carbide (SiC) has such excellent physical, chemical, and electronic properties that SiC based semiconductor electronics can operate at temperatures in excess of 600°C well beyond the high temperature limit for Si based semiconductor devices. SiC semiconductor devices have been demonstrated to be operable at temperatures as high as 600°C, but only in a probe-station environment partially because suitable packaging technology for high temperature (500°C and beyond) devices is still in development. One of the core technologies necessary for high temperature electronic packaging is semiconductor die-attach with low and stable electrical resistance. This paper discusses a low resistance die-attach method and the results of testing carried out at both room temperature and 500°C in air. A 1 mm2 SiC Schottky diode die was attached to aluminum nitride (AlN) and 96% pure alumina ceramic substrates using precious metal based thick-film material. The attached test die using this scheme survived both electronically and mechanically performance and stability tests at 500°C in oxidizing environment of air for 550 hours. The upper limit of electrical resistance of the die-attach interface estimated by forward I-V curves of an attached diode before and during heat treatment indicated stable and low attach-resistance at both room-temperature and 500°C over the entire 550 hours test period. The future durability tests are also discussed.

Electron-Beam Assisted CVD of Silicon Homoepitaxial Films

1988 ◽  
Vol 129 ◽  
Author(s):  
J. P. West ◽  
C. B. Fleddermann
Keyword(s):  
Electron Beam ◽  
Single Crystal Silicon ◽  
Beam Current ◽  
Silicon Substrates ◽  
Beam Diameter ◽  
Epitaxial Silicon ◽  
Large Area ◽  
Plasma Etch ◽  
Crystal Silicon

ABSTRACTThe use of a wide-area electron beam to aid the deposition of epitaxial silicon films has been studied. The electron beam used in this study is generated using a cold cathode, abnormal-glow discharge which allows a wide variation of electron energy and beam current. Depositions are performed on single crystal silicon substrates which are prepared using standard wet chemical silicon cleaning techniques and an in situ plasma etch using nitrogen tri-fluoride diluted in hydrogen. The beam diameter is approximately 10 cm and can readily be scaled up to accommodate larger diameters, allowing great potential for large area single wafer deposition. Using electron beams generated in this system, we have demonstrated enhanced growth rates and improved crystalline quality for films grown withelectronbeam enhancement.

TEM characterization of Au/Polysilicon interactions

1990 ◽  
Vol 48 (4) ◽  
pp. 650-651
Author(s):  
N. David Theodore ◽  
Leslie H. Allen ◽  
C. Barry Carter ◽  
James W. Mayer
Keyword(s):  
Solid Phase ◽  
Single Crystal Silicon ◽  
Chemical Vapor ◽  
Electrical Contacts ◽  
Silicon Substrates ◽  
Crystal Silicon ◽  
Transmission Electron ◽  
Polysilicon Films ◽  
The Stability

Metal/polysilicon investigations contribute to an understanding of issues relevant to the stability of electrical contacts in semiconductor devices. These investigations also contribute to an understanding of Si lateral solid-phase epitactic growth. Metals such as Au, Al and Ag form eutectics with Si. reactions in these metal/polysilicon systems lead to the formation of large-grain silicon. Of these systems, the Al/polysilicon system has been most extensively studied. In this study, the behavior upon thermal annealing of Au/polysilicon bilayers is investigated using cross-section transmission electron microscopy (XTEM). The unique feature of this system is that silicon grain-growth occurs at particularly low temperatures ∽300°C).Gold/polysilicon bilayers were fabricated on thermally oxidized single-crystal silicon substrates. Lowpressure chemical vapor deposition (LPCVD) at 620°C was used to obtain 100 to 400 nm polysilicon films. The surface of the polysilicon was cleaned with a buffered hydrofluoric acid solution. Gold was then thermally evaporated onto the samples.

scholarly journals Novel Abrasive-Impregnated Pads and Diamond Plates for the Grinding and Lapping of Single-Crystal Silicon Carbide Wafers

2021 ◽  
Vol 11 (4) ◽  
pp. 1783
Author(s):  
Ming-Yi Tsai ◽  
Kun-Ying Li ◽  
Sun-Yu Ji
Keyword(s):  
Silicon Carbide ◽  
Wear Rate ◽  
Single Crystal ◽  
Traditional Method ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Single Crystal Silicon ◽  
Crystal Silicon ◽  
Diamond Grit ◽  
Ceramic Binder

In this study, special ceramic grinding plates impregnated with diamond grit and other abrasives, as well as self-made lapping plates, were used to prepare the surface of single-crystal silicon carbide (SiC) wafers. This novel approach enhanced the process and reduced the final chemical mechanical planarization (CMP) polishing time. Two different grinding plates with pads impregnated with mixed abrasives were prepared: one with self-modified diamond + SiC and a ceramic binder and one with self-modified diamond + SiO2 + Al2O3 + SiC and a ceramic binder. The surface properties and removal rate of the SiC substrate were investigated and a comparison with the traditional method was conducted. The experimental results showed that the material removal rate (MRR) was higher for the SiC substrate with the mixed abrasive lapping plate than for the traditional method. The grinding wear rate could be reduced by 31.6%. The surface roughness of the samples polished using the diamond-impregnated lapping plate was markedly better than that of the samples polished using the copper plate. However, while the surface finish was better and the grinding efficiency was high, the wear rate of the mixed abrasive-impregnated polishing plates was high. This was a clear indication that this novel method was effective and could be used for SiC grinding and lapping.

scholarly journals Amorphous thin-film oxide power devices operating beyond bulk single-crystal silicon limit

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yuki Tsuruma ◽  
Emi Kawashima ◽  
Yoshikazu Nagasaki ◽  
Takashi Sekiya ◽  
Gaku Imamura ◽  
...  
Keyword(s):  
Thin Film ◽  
Single Crystal ◽  
Flexible Substrate ◽  
Single Crystal Silicon ◽  
Bulk Single Crystal ◽  
Next Generation ◽  
Power Devices ◽  
Large Area ◽  
Crystal Silicon ◽  
Amorphous Thin Film

AbstractPower devices (PD) are ubiquitous elements of the modern electronics industry that must satisfy the rigorous and diverse demands for robust power conversion systems that are essential for emerging technologies including Internet of Things (IoT), mobile electronics, and wearable devices. However, conventional PDs based on “bulk” and “single-crystal” semiconductors require high temperature (> 1000 °C) fabrication processing and a thick (typically a few tens to 100 μm) drift layer, thereby preventing their applications to compact devices, where PDs must be fabricated on a heat sensitive and flexible substrate. Here we report next-generation PDs based on “thin-films” of “amorphous” oxide semiconductors with the performance exceeding the silicon limit (a theoretical limit for a PD based on bulk single-crystal silicon). The breakthrough was achieved by the creation of an ideal Schottky interface without Fermi-level pinning at the interface, resulting in low specific on-resistance Ron,sp (< 1 × 10–4 Ω cm2) and high breakdown voltage VBD (~ 100 V). To demonstrate the unprecedented capability of the amorphous thin-film oxide power devices (ATOPs), we successfully fabricated a prototype on a flexible polyimide film, which is not compatible with the fabrication process of bulk single-crystal devices. The ATOP will play a central role in the development of next generation advanced technologies where devices require large area fabrication on flexible substrates and three-dimensional integration.

A Current Conduction Mechanism in Laser Recrystallized Silicon Metal-Oxide-Semiconductor Transistors

1983 ◽  
Vol 23 ◽  
Author(s):  
Han-Sheng Lee
Keyword(s):  
Conduction Mechanism ◽  
Single Crystal Silicon ◽  
Silicon Films ◽  
Oxide Semiconductor ◽  
Silicon Substrates ◽  
Mos Transistors ◽  
Crystal Silicon ◽  
Ion Laser ◽  
Argon Ion ◽  
A Current

ABSTRACTN-channel MOS transistors were fabricated on silicon films that had been recrystallized by an argon ion laser at different power levels. These transistors showed electrical characteristics similar, but somewhat inferior to those devices fabricated on single crystal silicon substrates. These differences are attributed to the presence of trapping states at the grain boundaries of the crystallites in the recrystallized silicon. A coulombic scattering model is presented to explain these differences. In the case of films annealed at low laser power, an additional factor of nonuniform trap state distribution is invoked to explain device characteristics. This model provides an adequate explanation for the observed transport properties of transistors fabricated from recrystallized silicon films.

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