Manipulation of Germanium Nanocrystals in a Tri-Layer Insulator Structure of a Metal-Insulator-Semiconductor Memory Device

2002 ◽  
Vol 728 ◽  
Author(s):  
L.W. Teo ◽  
C.L. Heng ◽  
V. Ho ◽  
M. Tay ◽  
W.K. Choi ◽  
...  

AbstractA metal-insulator-semiconductor (MIS) device that consists of germanium (Ge) nanocrystals embedded in a novel tri-layer insulator structure is proposed for memory applications [1]. The tri-layer structure comprises a thin (≈5nm) rapid thermal oxidation (RTO) silicon dioxide (SiO2) layer, a Ge+SiO2 middle layer (6 - 20 nm) deposited by RF co-sputtering technique and a RF-sputtered silicon dioxide capping layer. High-resolution transmission electron microscopy (HRTEM) results show that Ge nanocrystals of sizes ranging from 6 –20 nm were found after rapid thermal annealing of the trilayer structure at 1000°C for 300s. The electrical properties of these devices have been characterized using capacitance versus voltage (C-V) measurements. A significant hysteresis was observed in the C-V curves of these devices, indicating charge trapping in the composite insulator. Comparison with devices having similar tri-layer insulator structure, but with a pure sputtered oxide middle layer (i.e. minus the Ge nanocrystals), clearly indicated that the observed charge trapping is due to the presence of the Ge nanocrystals in the middle layer. The C-V measurements of devices without the capping SiO2 layer exhibited no significant hysteresis as compared to the embedded Ge nanocrystal tri-layer devices. The HRTEM micrographs showed that the presence of the capping oxide is critical in the formation of nanocrystals for this structure. By varying the thickness of the middle layer, it was found that the maximum nanocrystal size correlates well with the middle layer thickness. This indicates that the nanocrystals are well confined by the RTO oxide layer and the capping oxide layer. In addition, Ge nanocrystals formed using a thinner middle layer were found to be relatively uniform in size and distribution. This structure, therefore, offers a possibility of fabricating memory devices with controllable Ge nanocrystals size.

2016 ◽  
Vol 8 (20) ◽  
pp. 13140-13149 ◽  
Author(s):  
Peter F. Satterthwaite ◽  
Andrew G. Scheuermann ◽  
Paul K. Hurley ◽  
Christopher E. D. Chidsey ◽  
Paul C. McIntyre

2006 ◽  
Vol 937 ◽  
Author(s):  
M. Yun ◽  
M. Arif ◽  
S. Gangopadhyay ◽  
S. Guha

ABSTRACTPolyfluorenes (PFs) have emerged as a promising family of blue polymer light-emitting diodes (PLED) due to their high electroluminescence quantum yield. Metal-insulator-semiconductor (MIS) diodes are the two terminal analogues of thin film transistors sharing the same basic layer structure. We have investigated two different structures based on poly [9,9'-(di 2-ethylhexyl)fluorene] (PF2/6), a MIS diode and a hole-only PLED. The MIS diodes were fabricated with the PF2/6 layer on p+ Si /Al2O3 substrates, and were characterized by means of capacitance-voltage (C-V) measurements as a function of frequency. From C-V measurements, the unintentional doping density is evaluated as ∼5.7×1017 cm−3 at frequencies above 20 kHz. The interface trap density is estimated as ∼7.2×1011 eV−1cm−2 at 10 kHz. Current-voltage measurements of PF2/6-based PLEDs shows a shallow trap space-charge-limited conduction from which the energy of the traps and hole mobilities are estimated.


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