Effect of Al-content and Post Deposition Annealing on the Electrical Properties of Ultra-thin HfAlxOy Layers

2002 ◽  
Vol 745 ◽  
Author(s):  
R. J. Carter ◽  
W. Tsai ◽  
E. Young ◽  
M. Caymax ◽  
J. W. Maes ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Electrical Properties ◽  
Fixed Charge ◽  
Post Deposition Annealing ◽  
Al Content ◽  
Partial Pressures ◽  
High K ◽  
Flatband Voltage ◽  
High Al Content ◽  
Post Deposition

ABSTRACTScaled HfAlxOy/SiO2 stacks down to 1.5 nm EOT have been achieved. Although the addition of Al to the HfO2 matrix can be beneficial, it is observed that the benefit of using a Hf-aluminate is compromised if the film has a high Al-content. This is observed in terms of a dielectric constant close to that of pure Al2O3 (∼ 9) and a large amount of negative fixed charge in the film (∼ 1012 cm-2). Using oxygen post deposition anneals we have been able to reduce flatband voltage shifts associated with fixed charge as well as CV hysteresis. In terms of scaling, the benefit of using a high-k material is compromised if a SiO2 layer is also present in the gate stack. Therefore, it is necessary to perform an O2 PDA at moderate temperatures or in low O2 partial pressures in order to control the thickness of the interfacial oxide layer.

Investigation on the Thermal and Electrical Properties of Ti-Si-O Film Formed by the Composite Sputtering Deposition

2001 ◽  
Vol 670 ◽  
Author(s):  
Akira Nishiyama ◽  
Akio Kaneko ◽  
Masato Koyama ◽  
Yoshiki Kamata ◽  
Ikuo Fujiwara ◽  
...  
Keyword(s):  
Thin Films ◽  
Dielectric Constant ◽  
Phase Separation ◽  
Nanocrystalline Film ◽  
Post Deposition Annealing ◽  
Current Increase ◽  
Sputtering Deposition ◽  
Thermal And Electrical Properties ◽  
Sputter Deposited ◽  
Post Deposition

ABSTRACTTi-Si-O films were sputter deposited from TiO2+SiO2 composite targets with various SiO2 content. The phase separation occurred for every SiO2 content used in this experiment (from 14% to 75%) and it has been revealed that nanocrystalline (TiO2)1-x(SiO2)x films in which anatase TiO2 forms tiny grains were obtained when x in the film is larger than 0.26. The tiny grain was effective for suppressing the thermal grooving phenomenon of the thin films by the post deposition annealing which leads to the leakage current increase. The dielectric constant of the nanocrystalline film was varied with the SiO2 content from the value of the bulk anatase to SiO2.

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

2006 ◽  
Vol 9 (6) ◽  
pp. 1031-1036 ◽  
Author(s):  
Youhei Sugimoto ◽  
Hideto Adachi ◽  
Keisuke Yamamoto ◽  
Dong Wang ◽  
Hideharu Nakashima ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Plasma Oxidation ◽  
Post Deposition Annealing ◽  
High K ◽  
Post Deposition

Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition

2005 ◽  
Vol 44 (4B) ◽  
pp. 2230-2234 ◽  
Author(s):  
Hag-Ju Cho ◽  
Hye Lan Lee ◽  
Hong Bae Park ◽  
Taek Soo Jeon ◽  
Seong Geon Park ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Post Deposition Annealing ◽  
Layer Deposition ◽  
Post Deposition

Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing

2004 ◽  
Vol 811 ◽  
Author(s):  
Takeo Matsuki ◽  
Yasushi Akasaka ◽  
Kiyoshi Hayashi ◽  
Masataka Noguchi ◽  
Koji Yamashita ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Gate Insulator ◽  
Flash Lamp ◽  
Gate Electrode ◽  
Post Deposition Annealing ◽  
Hysteresis Width ◽  
High K ◽  
Mis Capacitors ◽  
Hysteresis Characteristics ◽  
Post Deposition

ABSTRACTA Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.

Effects of post deposition annealing atmosphere on interfacial and electrical properties of HfO2/Ge3N4 gate stacks

2019 ◽  
Vol 675 ◽  
pp. 16-22 ◽  
Author(s):  
Kumar Mallem ◽  
S.V. Jagadeesh Chandra ◽  
Minkyu Ju ◽  
Subhajit Dutta ◽  
Swagata Phanchanan ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Annealing Atmosphere ◽  
Gate Stacks ◽  
Post Deposition Annealing ◽  
Post Deposition
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