Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing

2004 ◽  
Vol 811 ◽  
Author(s):  
Takeo Matsuki ◽  
Yasushi Akasaka ◽  
Kiyoshi Hayashi ◽  
Masataka Noguchi ◽  
Koji Yamashita ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Gate Insulator ◽  
Flash Lamp ◽  
Gate Electrode ◽  
Post Deposition Annealing ◽  
Hysteresis Width ◽  
High K ◽  
Mis Capacitors ◽  
Hysteresis Characteristics ◽  
Post Deposition

ABSTRACTA Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.

Area Selective Flash Lamp Post-Deposition Annealing of High-k Film Using Si Photo Absorber for Metal Gate MISFETs with NiSi Source/Drain

2005 ◽  
Author(s):  
Takeo Matsuki ◽  
Isamu Nishimura ◽  
Yasushi Akasaka ◽  
Kiyoshi Hayashi ◽  
Masataka Noguchi ◽  
...  
Keyword(s):  
Flash Lamp ◽  
Metal Gate ◽  
Post Deposition Annealing ◽  
High K ◽  
Post Deposition

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

2006 ◽  
Vol 9 (6) ◽  
pp. 1031-1036 ◽  
Author(s):  
Youhei Sugimoto ◽  
Hideto Adachi ◽  
Keisuke Yamamoto ◽  
Dong Wang ◽  
Hideharu Nakashima ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Plasma Oxidation ◽  
Post Deposition Annealing ◽  
High K ◽  
Post Deposition

Synthesis and properties of nanocoral ZnO structures

2013 ◽  
Vol 1552 ◽  
pp. 113-118
Author(s):  
Michał A. Borysiewicz ◽  
Anna Baranowska-Korczyc ◽  
Marek Ekielski ◽  
Marek Wzorek ◽  
Elżbieta Dynowska ◽  
...  
Keyword(s):  
Magnetron Sputtering ◽  
Reactive Magnetron Sputtering ◽  
Reactive Magnetron ◽  
Gate Electrode ◽  
Post Deposition Annealing ◽  
Post Deposition

ABSTRACTNanocoral ZnO structures are fabricated by means of reactive magnetron sputtering with post deposition annealing. The films are polycrystalline with highly developed surfaces. Their application for biosensing is presented in the extended-gate FET approach where a nanocoral gate electrode is used to sense the pH of the solution and then the presence of BSA molecules.

Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing

2010 ◽  
Vol 50 (5) ◽  
pp. 618-621 ◽  
Author(s):  
Chia-Wei Hsu ◽  
Yean-Kuen Fang ◽  
Wen-Kuan Yeh ◽  
Chun-Yu Chen ◽  
Yen-Ting Chiang ◽  
...  
Keyword(s):  
Metal Gate ◽  
Post Deposition Annealing ◽  
Reliability Characteristics ◽  
High K ◽  
Post Deposition

Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures

2008 ◽  
Vol 600-603 ◽  
pp. 679-682 ◽  
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Post Deposition Annealing ◽  
Interface Quality ◽  
Channel Mobility ◽  
Capacitance Voltage ◽  
Mis Capacitors ◽  
Post Deposition ◽  
Time Lead

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

Stabilization of a very high-k crystalline ZrO2 phase by post deposition annealing of atomic layer deposited ZrO2/La2O3 dielectrics on germanium

2010 ◽  
Vol 256 (16) ◽  
pp. 5031-5034 ◽  
Author(s):  
S. Abermann ◽  
C. Henkel ◽  
O. Bethge ◽  
G. Pozzovivo ◽  
P. Klang ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Post Deposition Annealing ◽  
Zro2 Phase ◽  
High K ◽  
Very High ◽  
Post Deposition

Electrical Characteristics of Crystalline Gd2O3 Film on Si (111): Impacts of Growth Temperature and Post Deposition Annealing

2010 ◽  
Vol 1252 ◽  
Author(s):  
Gang Niu ◽  
Bertrand Vilquin ◽  
Nicolas Baboux ◽  
Guillaume Saint-Girons ◽  
Carole Plossu ◽  
...  
Keyword(s):  
Molecular Beam ◽  
Defect Density ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Optimal Temperature ◽  
Post Deposition Annealing ◽  
High K ◽  
Electrical Characterizations ◽  
Post Deposition

AbstractThis work reports on the epitaxial growth of crystalline high-k Gd2O3 on Si (111) by Molecular Beam Epitaxy (MBE) for CMOS gate application. Epitaxial Gd2O3 films of different thicknesses have been deposited on Si (111) between 650°C~750°C. Electrical characterizations reveal that the sample grown at the optimal temperature (700°C) presents an equivalent oxide thickness (EOT) of 0.73nm with a leakage current density of 3.6×10-2 A/cm2 at |Vg-VFB|=1V. Different Post deposition Annealing (PDA) treatments have been performed for the samples grown under optimal condition. The Gd2O3 films exhibit good stability and the PDA process can effectively reduce the defect density in the oxide layer, which results in higher performances of the Gd2O3/Si (111) capacitor.

Effect of Al-content and Post Deposition Annealing on the Electrical Properties of Ultra-thin HfAlxOy Layers

2002 ◽  
Vol 745 ◽  
Author(s):  
R. J. Carter ◽  
W. Tsai ◽  
E. Young ◽  
M. Caymax ◽  
J. W. Maes ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Electrical Properties ◽  
Fixed Charge ◽  
Post Deposition Annealing ◽  
Al Content ◽  
Partial Pressures ◽  
High K ◽  
Flatband Voltage ◽  
High Al Content ◽  
Post Deposition

ABSTRACTScaled HfAlxOy/SiO2 stacks down to 1.5 nm EOT have been achieved. Although the addition of Al to the HfO2 matrix can be beneficial, it is observed that the benefit of using a Hf-aluminate is compromised if the film has a high Al-content. This is observed in terms of a dielectric constant close to that of pure Al2O3 (∼ 9) and a large amount of negative fixed charge in the film (∼ 1012 cm-2). Using oxygen post deposition anneals we have been able to reduce flatband voltage shifts associated with fixed charge as well as CV hysteresis. In terms of scaling, the benefit of using a high-k material is compromised if a SiO2 layer is also present in the gate stack. Therefore, it is necessary to perform an O2 PDA at moderate temperatures or in low O2 partial pressures in order to control the thickness of the interfacial oxide layer.

4H-SiC MOSFETs Using Thermal Oxidized Ta2Si Films as High-k Gate Dielectric

2005 ◽  
Vol 483-485 ◽  
pp. 713-716 ◽  
Author(s):  
Amador Pérez-Tomás ◽  
Phillippe Godignon ◽  
Narcis Mestres ◽  
Josep Montserrat ◽  
José Millan
Keyword(s):  
Dielectric Constant ◽  
Dielectric Layer ◽  
Room Temperature ◽  
Gate Dielectric ◽  
Gate Insulator ◽  
High K ◽  
Dry Oxidation ◽  
High K Dielectric ◽  
Si Films ◽  
Mis Capacitors

Oxidized Ta2Si layers have been used as high-k dielectric layer for 4H-SiC MOSFETs. The gate insulator was grown by dry oxidation of 40nm deposited Ta2Si during 1h at 1050oC. The dielectric constant obtained from 4H-SiC MIS capacitors is ~20 with an insulator thickness of 150nm. These devices exhibit adequate subthreshold, saturation and drive characteristics. For the MOSFETs fabricated on a p-implanted and annealed region, a peak mobility up to 45cm2/Vs has been extracted. The specific on-resistance of this device is 29mW·cm2 at room temperature with VDS=0.2V and VGS=14V.

Sign in / Sign up

Export Citation Format

Share Document