Minimization of Binary Decision Diagrams for Systems of Completely Defined Boolean Functions using Algebraic Representations of Cofactors

2021 ◽  
Vol 27 (8) ◽  
pp. 395-408
Author(s):  
P. N. Bibilo ◽  
◽  
V. I. Romanov ◽  
Keyword(s):  
Integrated Circuits ◽  
Boolean Functions ◽  
Logic Gates ◽  
Optimization Criterion ◽  
Combinational Circuits ◽  
Expansion Formula ◽  
Binary Decision ◽  
Digital Vlsi ◽  
Multilevel Representations ◽  
Algebraic Representations

In design systems for digital VLSI (very large integrated circuits), the BDD is used for VLSI verification, as well as for technologically independent optimization, performed as the first stage in the synthesis of logic circuits in various technological bases. BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph corresponds to the complete or reduced Shannon expansion formula. Having constructed BDD representation for systems of Boolean functions, it is possible to perform additional logical optimization based on the proposed method of searching for algebraic representations of cofactors (subfunctions) of the same BDD level in the form of a disjunction or conjunction of other cofactors of this BDD level. The method allows to reduce the number of literals by replacing the Shannon expansion formulas with simpler formulas that are disjunctions or conjunctions of cofactors, and to reduce the number of literals in specifying a system of Boolean functions. The number of literals in algebraic multilevel representations of systems of fully defined Boolean functions is the main optimization criterion in the synthesis of combinational circuits from library logic gates.

scholarly journals Digital logic gates in soft, conductive mechanical metamaterials

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Charles El Helou ◽  
Philip R. Buskohl ◽  
Christopher E. Tabor ◽  
Ryan L. Harne
Keyword(s):  
Integrated Circuits ◽  
Electronic Materials ◽  
Polymer Networks ◽  
Conductive Polymer ◽  
Network Connectivity ◽  
Logic Gates ◽  
Boolean Logic ◽  
Digital Logic ◽  
Mechanical Metamaterials ◽  
Logic Operations

AbstractIntegrated circuits utilize networked logic gates to compute Boolean logic operations that are the foundation of modern computation and electronics. With the emergence of flexible electronic materials and devices, an opportunity exists to formulate digital logic from compliant, conductive materials. Here, we introduce a general method of leveraging cellular, mechanical metamaterials composed of conductive polymers to realize all digital logic gates and gate assemblies. We establish a method for applying conductive polymer networks to metamaterial constituents and correlate mechanical buckling modes with network connectivity. With this foundation, each of the conventional logic gates is realized in an equivalent mechanical metamaterial, leading to soft, conductive matter that thinks about applied mechanical stress. These findings may advance the growing fields of soft robotics and smart mechanical matter, and may be leveraged across length scales and physics.

scholarly journals A Novel Graphical Technique for Combinational Logic Representation and Optimization

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-12
Author(s):  
Vedhas Pandit ◽  
Björn Schuller
Keyword(s):  
Boolean Functions ◽  
Discrete Systems ◽  
Boolean Logic ◽  
Decision Diagrams ◽  
New Paradigm ◽  
Binary Decision ◽  
Graphical Technique ◽  
A New Technique ◽  
Logic Functions ◽  
Logical Functions

We present a new technique for defining, analysing, and simplifying digital functions, through hand-calculations, easily demonstrable therefore in the classrooms. It can be extended to represent discrete systems beyond the Boolean logic. The method is graphical in nature and provides complete ‘‘implementation-free” description of the logical functions, similar to binary decision diagrams (BDDs) and Karnaugh-maps (K-maps). Transforming a function into the proposed representations (also the inverse) is a very intuitive process, easy enough that a person can hand-calculate these transformations. The algorithmic nature allows for its computing-based implementations. Because the proposed technique effectively transforms a function into a scatter plot, it is possible to represent multiple functions simultaneously. Usability of the method, therefore, is constrained neither by the number of inputs of the function nor by its outputs in theory. This, being a new paradigm, offers a lot of scope for further research. Here, we put forward a few of the strategies invented so far for using the proposed representation for simplifying the logic functions. Finally, we present extensions of the method: one that extends its applicability to multivalued discrete systems beyond Boolean functions and the other that represents the variants in terms of the coordinate system in use.

scholarly journals An n log n Algorithm for Online BDD Refinement

1995 ◽  
Vol 2 (29) ◽  
Author(s):  
Nils Klarlund
Keyword(s):  
Fixed Points ◽  
Boolean Functions ◽  
Linear Time ◽  
Canonical Representation ◽  
Decision Diagrams ◽  
Total Size ◽  
Binary Decision ◽  
Algebraic Framework ◽  
Verification Systems ◽  
Minimal Fixed Point

Binary Decision Diagrams are in widespread use in verification systems<br />for the canonical representation of Boolean functions. A BDD representing<br />a function phi : B^nu -> N can easily be reduced to its canonical form in<br />linear time.<br />In this paper, we consider a natural online BDD refinement problem<br />and show that it can be solved in O(n log n) if n bounds the size of the<br />BDD and the total size of update operations.<br />We argue that BDDs in an algebraic framework should be understood<br />as minimal fixed points superimposed on maximal fixed points. We propose<br />a technique of controlled growth of equivalence classes to make the<br />minimal fixed point calculations be carried out efficiently. Our algorithm<br />is based on a new understanding of the interplay between the splitting<br />and growing of classes of nodes.<br />We apply our algorithm to show that automata with exponentially<br />large, but implicitly represented alphabets, can be minimized in time<br />O(n log n), where n is the total number of BDD nodes representing the<br />automaton.

scholarly journals Efficient and Compact SR-flip Flop Optical Memory Based Photonic Crystals Platform

2021 ◽  
Author(s):  
Amr Hassan ◽  
Nihal F. F. Areed ◽  
Salah S. A. Obayya ◽  
Hamdi El Mikati
Keyword(s):  
Integrated Circuits ◽  
Optical Memory ◽  
Logic Gates ◽  
Power Input ◽  
Small Dimension ◽  
Square Lattice ◽  
Optical Logic ◽  
Flip Flop ◽  
Compact Size ◽  
Multiple Devices

Abstract The paper presents a different type of designing methods and operational improvements of the optical logic memory SR-flip flop (SR-FF). The proposed optical memory SR-FF is based on two optical NOR logic gates which use two-dimension (2D) photonic crystal (PhC) with a square lattice of silicon (Si) dielectric rods. The structure has a switching time in only a few Picoseconds with little power input and very little power loss. The proposed optical memory SR-FF has a small dimension 38x22 μm2 which makes it one of the best optimized and most practical structures to be used in all photonic integrated circuits (PICs). The ultra-compact size enables the possibility of multiple devices to be embedded in a single PIC chip.

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

Spin Logic Gates Operated by Protonation and Magnetism in Molecular Combinational Circuits

2019 ◽  
pp. 1900057 ◽  
Author(s):  
Wenkai Zhao ◽  
Dongqing Zou ◽  
Zhaopeng Sun ◽  
Yuqing Xu ◽  
Guomin Ji ◽  
...  
Keyword(s):  
Logic Gates ◽  
Combinational Circuits ◽  
Spin Logic

ORDERED BINARY DECISION DIAGRAMS AND THEIR SIGNIFICANCE IN COMPUTER-AIDED DESIGN OF VLSI CIRCUITS

1999 ◽  
Vol 09 (03n04) ◽  
pp. 181-198 ◽  
Author(s):  
CHRISTOPH MEINEL ◽  
THORSTEN THEOBALD
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Binary Decision Diagrams ◽  
Basic Research ◽  
Vlsi Circuits ◽  
Decision Diagrams ◽  
Ordered Binary Decision Diagrams ◽  
Binary Decision ◽  
Computer Aided ◽  
Aided Design

Many problems in computer-aided design of highly integrated circuits (CAD for VLSI) can be transformed to the task of manipulating objects over finite domains. The efficiency of these operations depends substantially on the chosen data structures. In the last years, ordered binary decision diagrams (OBDDs) have proven to be a very efficient data structure in this context. Here, we give a survey on these developments and stress the deep interactions between basic research and practically relevant applied research with its immediate impact on the performance improvement of modern CAD design and verification tools.

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