scholarly journals Efficient and Compact SR-flip Flop Optical Memory Based Photonic Crystals Platform

2021 ◽  
Author(s):  
Amr Hassan ◽  
Nihal F. F. Areed ◽  
Salah S. A. Obayya ◽  
Hamdi El Mikati
Keyword(s):  
Integrated Circuits ◽  
Optical Memory ◽  
Logic Gates ◽  
Power Input ◽  
Small Dimension ◽  
Square Lattice ◽  
Optical Logic ◽  
Flip Flop ◽  
Compact Size ◽  
Multiple Devices

Abstract The paper presents a different type of designing methods and operational improvements of the optical logic memory SR-flip flop (SR-FF). The proposed optical memory SR-FF is based on two optical NOR logic gates which use two-dimension (2D) photonic crystal (PhC) with a square lattice of silicon (Si) dielectric rods. The structure has a switching time in only a few Picoseconds with little power input and very little power loss. The proposed optical memory SR-FF has a small dimension 38x22 μm2 which makes it one of the best optimized and most practical structures to be used in all photonic integrated circuits (PICs). The ultra-compact size enables the possibility of multiple devices to be embedded in a single PIC chip.

scholarly journals Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550011
Author(s):  
Neeraja Jagadeesan ◽  
B. Saman ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. Jain
Keyword(s):  
Integrated Circuits ◽  
Quantum Well ◽  
Logic Gates ◽  
Digital Integrated Circuits ◽  
Short Channel ◽  
Flip Flop ◽  
Coupled Channels ◽  
Threshold Voltages ◽  
Sequential Logic ◽  
Quantum Well Devices

The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

Multifunctional logic gates based on silicon hybrid plasmonic waveguides

2018 ◽  
Vol 32 (02) ◽  
pp. 1850008 ◽  
Author(s):  
Luna Cui ◽  
Li Yu
Keyword(s):  
Integrated Circuits ◽  
Logic Gates ◽  
Threshold Value ◽  
Multimode Interference ◽  
Plasmonic Waveguides ◽  
Optical Logic ◽  
Optical Logic Gates ◽  
Input Signals ◽  
All Optical ◽  
Hybrid Plasmonic Waveguides

Nano-scale Multifunctional Logic Gates based on Si hybrid plasmonic waveguides (HPWGs) are designed by utilizing the multimode interference (MMI) effect. The proposed device is composed of three input waveguides, three output waveguides and an MMI waveguide. The functional size of the device is only 1000 nm × 3200 nm, which is much smaller than traditional Si-based all-optical logic gates. By setting different input signals and selecting suitable threshold value, OR, AND, XOR and NOT gates are achieved simultaneously or individually in a single device. This may provide a way for ultrahigh speed signal processing and future nanophotonic integrated circuits.

scholarly journals Enhanced All-Optical Y-Shaped Plasmonic OR, NOR And NAND Gate Models, Analyses, And Simulation For High Speed Computations

2021 ◽  
Author(s):  
Ipshitha Charles ◽  
Alluru Sreev ◽  
SabbiVamshi Krishna ◽  
Sandip Swarnakar ◽  
Santosh Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Extinction Ratio ◽  
Logic Gates ◽  
Nand Gate ◽  
Optical Logic ◽  
Metal Insulator Metal ◽  
All Optical ◽  
A New Technique ◽  
Complex Circuits

Abstract In this digital era, all-optical logic gates (OLGs) proved its effectiveness in execution of high-speed computations. A unique construction of an all-optical OR, NOR, NAND gates based on the notion of power combiner employing metal–insulator–metal (MIM) waveguide in the Y-shape in a minimal imprint of 6.2 µm × 3 µm is presented and the structure is evaluated by finite-difference time-domain (FDTD) technique. The insertion loss (IL) and extinction-ratio (ER) for proposed model are 6 dB and 27.76 dB for NAND gate, 2 dB and 20.35 dB for NOR gate and 6 dB and 24.10 dB respectively. The simplified model is used in the construction of complex circuits to achieve greater efficiency, which contributes to the emergence of a new technique for designing plasmonic integrated circuits.

scholarly journals Programmable all-optical logic gates based on semiconductor optical amplifiers

1970 ◽  
Vol 1 ◽  
pp. 37-38
Author(s):  
Félix Sotelo ◽  
José Antonio Altabás ◽  
Miguel Cabezón ◽  
Ignacio Garcés
Keyword(s):  
Integrated Circuits ◽  
Optical Amplifiers ◽  
Photonic Integrated Circuits ◽  
Semiconductor Optical Amplifiers ◽  
Logic Gates ◽  
Proof Of Concept ◽  
Optical Logic ◽  
All Optical ◽  
Programmable Logic Devices ◽  
Programmable Devices

In this paper, we discuss the feasibility of optical programmable logic devices based on non-linear processing with semiconductor optical amplifiers. We carried out simulations of the architecture of an all-optical 4-bit Look-up Table, which is the basic logic element of larger-scale programmable devices, and experimental results from a proof-of-concept setup using commercially available devices.Experimental work with photonic integrated circuits to assess the feasibility of integration of such architectures is also presented.

scholarly journals Enhanced All-optical Y-shaped Plasmonic NAND Gate Model, Analysis, and Simulation for High Speed Computations

2021 ◽  
Author(s):  
Ipshitha Charles ◽  
Alluru Sreev ◽  
SabbiVamshi Krishna ◽  
Sandip Swarnakar ◽  
Santosh Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Extinction Ratio ◽  
Logic Gates ◽  
Nand Gate ◽  
Optical Logic ◽  
Metal Insulator Metal ◽  
All Optical ◽  
A New Technique ◽  
Complex Circuits

Abstract In this digital era, all-optical logic gates (OLGs) proved its effectiveness in execution of high-speed computations. A unique construction for all optical NAND gate based on the notion of power combiner employing metal–insulator–metal (MIM) waveguide in the Y-shape in a minimal imprint of 6.2 µm × 3 µm is presented and the structure is evaluated by finite-difference time-domain (FDTD) technique. The insertion loss (IL) and extinction-ratio (ER) for proposed model are 6 dB and 27.76 dB. The simplified model is used in the construction of complex circuits to achieve greater efficiency, which contributes to the emergence of a new technique for designing plasmonic integrated circuits.

Impact of technological advances and architectural insights on the design of optical computers

1984 ◽  
Vol 313 (1525) ◽  
pp. 205-211 ◽  
Keyword(s):  
Computer Architecture ◽  
Optical Memory ◽  
Logic Gates ◽  
Optical Nonlinearities ◽  
Optical Logic ◽  
Clock Skew ◽  
Large Bandwidth ◽  
Communication Problems ◽  
Technological Advances ◽  
Optical Computers

Communication problems such as interconnection bandwidth, clock skew, and connectivity are restricting computational throughput. Bandwidth and clock skew problems limit the speed and add to the design complexity of a processor. Constrained connectivity forces much of the speed of a processor to be used to compensate for the limited number of interconnections. . Philosophically, the large bandwidth, innate parallelism and non-interfering propagation of optics offer mechanisms for overcoming these communication problems. The difficulty in exploiting these capabilities has been the absence of suitable optical logic and memory devices. Advances in optical nonlinearities offer the possibility of cascadable optical logic gates that are competitive with electronics. Advances in computer architecture can be used to simplify the optical memory requirements and utilize the large bandwidth, parallel, non-interfering communications of optics.

scholarly journals Circuit Techniques in GaN Technology for High-Temperature Environments

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 42
Author(s):  
Ahmad Hassan ◽  
Jean-Paul Noël ◽  
Yvon Savaria ◽  
Mohamad Sawan
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
National Research Council ◽  
Logic Gates ◽  
Voltage Reference ◽  
Flip Flop ◽  
Wide Range ◽  
Circuit Techniques ◽  
First Time

As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilling. More than 15 integrated circuits were implemented and tested. We performed the HT characterization of passive elements integrated in GaN500 including resistors, capacitors, and inductors up to 600 °C. Moreover, we developed for the first time several digital circuits based on GaN500 technology, including logic gates (NOT, NAND, NOR), ring oscillators, D Flip-Flop, Delay circuits, and voltage reference circuits. The tested circuits are fabricated on a 4 mm × 4 mm chip to validate their functionality over a wide range of temperatures. The logic gates show functionality at HT over 400 °C, while the voltage reference circuits remain stable up to 550 °C.

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