scholarly journals Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology

2021 ◽  
Vol 12 (3) ◽  
pp. 5720-5725
Author(s):  
A.S Keerthi Nayani Et. al.
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Ripple Carry Adder ◽  
Xnor Gate ◽  
Low Power Cmos

The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

Novel low power full adder cells in 180nm CMOS technology

2009 ◽  
Author(s):  
Dan Wang ◽  
Maofeng Yang ◽  
Wu Cheng ◽  
Xuguang Guan ◽  
Zhangming Zhu ◽  
...  
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Cmos Technology

Ultrathin DPN STI SiON liner for 40nm low-power CMOS technology

2010 ◽  
Vol 54 (5) ◽  
pp. 564-567 ◽  
Author(s):  
Chan-Yuan Hu ◽  
Jone F. Chen ◽  
Shih-Chih Chen ◽  
Shoou-Jinn Chang ◽  
Kay-Ming Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Low Power Cmos
Sign in / Sign up

Export Citation Format

Share Document