scholarly journals Hetero - Gate Oxide Dual Metal Vertical Tunnel FET

2021 ◽  
Keyword(s):  
Gate Oxide ◽  
Tunnel Fet ◽  
Dual Metal

Abstract The authors have requested that this preprint be withdrawn due to erroneous posting.

scholarly journals Hetero - Gate Oxide Dual Metal Vertical Tunnel FET

2021 ◽  
Author(s):  
Priyanka Karmakar ◽  
P K Sahu
Keyword(s):  
Gate Oxide ◽  
Double Gate ◽  
Subthreshold Slope ◽  
Device Design ◽  
Metal Gate ◽  
Tunneling Barrier ◽  
Tunnel Fet ◽  
Dc Characteristics ◽  
Dual Metal ◽  
Silicon Based

Abstract A Silicon based Vertical Dual metal Double gate Tunnel FET (Si-VDMDGTFET) has been proposed and simulated in Sentaurus TCAD tool with improved DC and analog/RF characteristics. The vertical In-line tunneling dominates in the proposed device which results in better subthreshold slope (SS). The vertical in-line tunneling tunes the tunneling barrier and eventually controls the ON current. The dual metal gate and the heterogeneous gate stack oxide within the proposed device design gives the mouldability for controlling and improving the DC characteristics such as ON current, OFF current. The analog/RF behaviour of the proposed device has been calculated and compared with conventional lateral Silicon based dual metal double gate Tunnel FET furthermore it is seen that the proposed device outperforms the conventional lateral device.

scholarly journals Impactful Study of F-shaped Tunnel FET

2021 ◽  
Author(s):  
PRABHAT SINGH ◽  
DHARMENDRA SINGH YADAV
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Gate Oxide ◽  
Crowding Effect ◽  
Turn On ◽  
Tunnel Fet ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

Abstract In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is proposed and investigated. The impact of thickness of the source region and lateral tunneling length between the gate oxide and edge of the source region on analog and radio frequency parameters are investigated with appropriate source and drain lateral length through the 2D-TCAD tool. The slender shape of the source enhanced the electric le crowding effect at the corners of the source region which reflect in term of high On-current (Ion). The Ion of proposed device is increased up to 10-4 A=μm with reduced sub-threshold swing (SS) is 7.3 mV/decade and minimum turn-ON voltage (Von = 0.28 V). The analog/RF parameters of SG-FC-TFET are optimized.

Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

2021 ◽  
Author(s):  
Amit Kumar ◽  
Anil Kumar Rajput ◽  
Manisha Pattanaik ◽  
Pankaj Srivast
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Analytical Modelling ◽  
Device Performance ◽  
Oxide Material ◽  
Metal Gate ◽  
Drain Region ◽  
Dual Metal ◽  
Nitride Oxide ◽  
Potential Threshold

Abstract In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all around FET (DM-NO GAAFET) respectively, in which surface potential, threshold voltage, and DIBL are modelled for both the devices. The proposed models are validated by comparing DM-NO GAAFET with DM-VO GAAFET. DM-NO GAAFET shows the better device performance than DM-VO GAAFET as the threshold voltage increased by 10% and DIBL decreased by 50% in simulated as well as analytical results. The obtained results are having very close agreement with simulated results for both the GAAFETs.

Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current

2014 ◽  
Vol 61 (3) ◽  
pp. 776-784 ◽  
Author(s):  
Giovanni Betti Beneventi ◽  
Elena Gnani ◽  
Antonio Gnudi ◽  
Susanna Reggiani ◽  
Giorgio Baccarani
Keyword(s):  
Metal Gate ◽  
Turn On ◽  
Tunnel Fet ◽  
Dual Metal
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