Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

The length of Source/Drain (S/D) extension (LSDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer LSDE pFinFET provides a larger series resistance and degrades the drive current (IDS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter LSDE plus the shorter channel length demonstrates a higher trans-conductance (Gm) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer LSDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current. DOI: 10.21883/FTP.2017.12.45190.8421

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Effect of Channel Length and Dielectric Constant on Carbon Nanotube FET to Evaluate the Device Performance

2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) ◽

10.1109/iementech51367.2020.9270118 ◽

2020 ◽

Author(s):

Md. Abid Hasan Shanto ◽

Naimur R. Niloy ◽

Raian Islam ◽

Muzaddidul I. Chowdhury ◽

Murad Mehrab Abrar ◽

...

Keyword(s):

Dielectric Constant ◽

Carbon Nanotube ◽

Channel Length ◽

Device Performance ◽

Carbon Nanotube Fet

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3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect

Indonesian Journal of Electrical Engineering and Computer Science ◽

10.11591/ijeecs.v12.i3.pp1358-1365 ◽

2018 ◽

Vol 12 (3) ◽

pp. 1358

Author(s):

Ameer F. Roslan ◽

F. Salehuddin ◽

A.S. M.Zain ◽

K.E. Kaharudin ◽

H. Hazura ◽

...

Keyword(s):

Leakage Current ◽

Electrical Characterization ◽

Channel Length ◽

Double Gate ◽

Short Channel ◽

3D Design ◽

Drive Current ◽

Minimum Requirement ◽

Technology Roadmap ◽

Low Performance

<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>

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Subthreshold swing model using scale length for sub-10 nm junction-based double-gate MOSFETs

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v10i2.pp1747-1754 ◽

2020 ◽

Vol 10 (2) ◽

pp. 1747

Author(s):

Hakkee Jung

Keyword(s):

Analytical Model ◽

Potential Distribution ◽

Geometric Mean ◽

Oxide Thickness ◽

Channel Length ◽

Subthreshold Swing ◽

Double Gate ◽

Silicon Thickness ◽

The Relationship ◽

Scale Length

We propose an analytical model for subthreshold swing using scale length for sub-10 nm double gate (DG) MOSFETs. When the order of the calculation for the series type potential distribution is increased it is possible to obtain accuracy, but there is a problem that the calculation becomes large. Using only the first order calculation of potential distribution, we derive the scale length λ1 and use it to obtain an analytical model of subthreshold swing. The findings show this subthreshold swing model is in concordance with a 2D simulation. The relationship between the channel length and silicon thickness, which can analyze the subthreshold swing using λ1, is derived by the relationship between the scale length and the geometric mean of the silicon and oxide thickness. If the silicon thickness and oxide film thickness satisfy the condition of (Lg-0.215)/6.38 > tsi(=tox), it is found that the result of this model agrees with the results using higher order calculations, within a 4% error range.

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A new method to determine effective channel length, series resistance and threshold voltage

Proceedings of International Conference on Microelectronic Test Structures ◽

10.1109/icmts.1996.535635 ◽

2002 ◽

Cited By ~ 5

Author(s):

M. Sasaki ◽

H. Ito ◽

T. Horiuchi

Keyword(s):

Threshold Voltage ◽

Series Resistance ◽

Channel Length ◽

New Method ◽

Effective Channel

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Optical Filter for Fabricating Self-Aligned Amorphous Si TFTS

MRS Proceedings ◽

10.1557/proc-557-677 ◽

1999 ◽

Vol 557 ◽

Cited By ~ 5

Author(s):

P. Mei ◽

J. P Lu ◽

C. Chua ◽

J. Ho ◽

Y. Wang ◽

...

Keyword(s):

High Performance ◽

Uv Light ◽

Optical Filter ◽

Device Performance ◽

Gate Electrode ◽

Large Area ◽

New Process ◽

Amorphous Si ◽

Difficult Challenge ◽

Channel Region

AbstractSelf-aligned structures for bottom-gate amorphous Si TFTs provide a number of advantages, including reduced parasitic capacitance, smaller device dimensions, and improved uniformity in device performance for large-area electronics. A difficult challenge in making self-aligned TFT structures is the necessity of making source/drain contacts that exhibit low contact resistances and that are precisely aligned relative to the gate electrode. In this article, we describe a novel process for fabricating self-aligned amorphous Si TFTs. This process utilizes a pulsed excimer laser (308 nm) to dope or to activate dopants in a-Si to form the source/drain contacts. An important feature of the device design is an optical filter to protect the a-Si channel region from radiation damage during the 308 nm laser process. However, the optical filter allows the transmission of the uv light for lithography exposure from the backside of the substrate to align the channel region with the gate electrode. This new process enables the fabrication of high performance self-aligned a-Si TFTs with poly-Si source and drain contacts.

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