Hyper-codes, high-performance low-complexity error-correcting codes.

Hypergraph product codes are a class of constant-rate quantum low-density parity-check (LDPC) codes equipped with a linear-time decoder called small-set-flip (SSF). This decoder displays sub-optimal performance in practice and requires very large error correcting codes to be effective. In this work, we present new hybrid decoders that combine the belief propagation (BP) algorithm with the SSF decoder. We present the results of numerical simulations when codes are subject to independent bit-flip and phase-flip errors. We provide evidence that the threshold of these codes is roughly 7.5% assuming an ideal syndrome extraction, and remains close to 3% in the presence of syndrome noise. This result subsumes and significantly improves upon an earlier work by Grospellier and Krishna (arXiv:1810.03681). The low-complexity high-performance of these heuristic decoders suggests that decoding should not be a substantial difficulty when moving from zero-rate surface codes to constant-rate LDPC codes and gives a further hint that such codes are well-worth investigating in the context of building large universal quantum computers.

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High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽

10.3390/sym13040700 ◽

2021 ◽

Vol 13 (4) ◽

pp. 700

Author(s):

Yufei Zhu ◽

Zuocheng Xing ◽

Zerun Li ◽

Yang Zhang ◽

Yifan Hu

Keyword(s):

High Performance ◽

Ldpc Codes ◽

Low Complexity ◽

Cmos Technology ◽

Area Efficiency ◽

Prior Art ◽

New Radio ◽

High Area ◽

Significant Area ◽

Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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Application-based fault tolerance techniques for sparse matrix solvers

The International Journal of High Performance Computing Applications ◽

10.1177/1094342017694946 ◽

2017 ◽

Vol 32 (5) ◽

pp. 627-640

Author(s):

Simon McIntosh–Smith ◽

Rob Hunt ◽

James Price ◽

Alex Warwick Vesztrocy

Keyword(s):

Fault Tolerance ◽

High Performance Computing ◽

High Performance ◽

Sparse Matrix ◽

Sparse Matrices ◽

Error Correcting Codes ◽

Computing Systems ◽

Hardware Costs ◽

Extreme Scale ◽

Performance Computing

High-performance computing systems continue to increase in size in the quest for ever higher performance. The resulting increased electronic component count, coupled with the decrease in feature sizes of the silicon manufacturing processes used to build these components, may result in future exascale systems being more susceptible to soft errors caused by cosmic radiation than in current high-performance computing systems. Through the use of techniques such as hardware-based error-correcting codes and checkpoint-restart, many of these faults can be mitigated at the cost of increased hardware overhead, run-time, and energy consumption that can be as much as 10–20%. Some predictions expect these overheads to continue to grow over time. For extreme scale systems, these overheads will represent megawatts of power consumption and millions of dollars of additional hardware costs, which could potentially be avoided with more sophisticated fault-tolerance techniques. In this paper we present new software-based fault tolerance techniques that can be applied to one of the most important classes of software in high-performance computing: iterative sparse matrix solvers. Our new techniques enables us to exploit knowledge of the structure of sparse matrices in such a way as to improve the performance, energy efficiency, and fault tolerance of the overall solution.

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A novel low-complexity and high-performance frame-skipping transcoder in dct domain

IEEE Transactions on Consumer Electronics ◽

10.1109/tce.2005.1561860 ◽

2005 ◽

Vol 51 (4) ◽

pp. 1306-1312 ◽

Cited By ~ 5

Author(s):

Chunrong Zhang ◽

Shibao Zheng ◽

Chi Yuan ◽

Feng Wang

Keyword(s):

High Performance ◽

Low Complexity ◽

Dct Domain ◽

Performance Frame

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- Design of High-Performance Error-Correcting Codes Using FPGA

Reconfigurable Logic ◽

10.1201/b19388-21 ◽

2018 ◽

pp. 380-403

Keyword(s):

High Performance ◽

Error Correcting Codes ◽

Performance Error

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Low-Complexity High-Performance Cyclic Caching for Large MISO Systems

IEEE Transactions on Wireless Communications ◽

10.1109/twc.2021.3119772 ◽

2021 ◽

pp. 1-1

Author(s):

Mohammad Javad Salehi ◽

Emanuele Parrinello ◽

Seyed Pooya Shariatpanahi ◽

Petros Elia ◽

Antti Tolli

Keyword(s):

High Performance ◽

Low Complexity

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Efficient Low-Complexity Digital Predistortion for Power Amplifier Linearization

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v6i3.pp1096-1105 ◽

2016 ◽

Vol 6 (3) ◽

pp. 1096

Author(s):

Siba Monther Yousif ◽

Roslina M. Sidek ◽

Anwer Sabah Mekki ◽

Nasri Sulaiman ◽

Pooria Varahram

Keyword(s):

Power Amplifier ◽

High Performance ◽

Low Complexity ◽

Memory Effects ◽

Model Complexity ◽

Model Parameters ◽

Digital Predistortion ◽

Nonlinear Memory ◽

Proposed Model ◽

Code Division Multiple

<span lang="EN-US">In this paper, a low-complexity model is proposed for linearizing power amplifiers with memory effects using the digital predistortion (DPD) technique. In the proposed model, the linear, low-order nonlinear and high-order nonlinear memory effects are computed separately to provide flexibility in controlling the model parameters so that both high performance and low model complexity can be achieved. The performance of the proposed model is assessed based on experimental measurements of a commercial class AB power amplifier by applying a single-carrier wideband code division multiple access (WCDMA) signal. The linearity performance and the model complexity of the proposed model are compared with the memory polynomial (MP) model and the DPD with single-feedback model. The experimental results show that the proposed model outperforms the latter model by 5 dB in terms of adjacent channel leakage power ratio (ACLR) with comparable complexity. Compared to MP model, the proposed model shows improved ACLR performance by 10.8 dB with a reduction in the complexity by 17% in terms of number of floating-point operations (FLOPs) and 18% in terms of number of model coefficients.</span>

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Orthogonal Time Sequency Multiplexing Modulation

10.36227/techrxiv.13580201.v1 ◽

2021 ◽

Author(s):

Tharaj Thaj ◽

Emanuele Viterbo

Keyword(s):

Time Domain ◽

Orthogonal Frequency Division Multiplexing ◽

High Performance ◽

High Mobility ◽

Low Complexity ◽

Modulation Scheme ◽

Frequency Space ◽

Time Frequency ◽

Single Carrier ◽

The Time Domain

This paper proposes <i>orthogonal time sequency multiplexing</i> (OTSM), a novel single carrier modulation scheme based on the well known Walsh-Hadamard transform (WHT) combined with row-column interleaving, and zero padding (ZP) between blocks in the time-domain. The information symbols in OTSM are multiplexed in the delay and sequency domain using a cascade of time-division and Walsh-Hadamard (sequency) multiplexing. By using the WHT for transmission and reception, the modulation and demodulation steps do not require any complex multiplications. We then propose two low-complexity detectors: (i) a simpler non-iterative detector based on a single tap minimum mean square time-frequency domain equalizer and (ii) an iterative time-domain detector. We demonstrate, via numerical simulations, that the proposed modulation scheme offers high performance gains over orthogonal frequency division multiplexing (OFDM) and exhibits the same performance of orthogonal time frequency space (OTFS) modulation, but with lower complexity. In proposing OTSM, along with simple detection schemes, we offer the lowest complexity solution to achieving reliable communication in high mobility wireless channels, as compared to the available schemes published so far in the literature.

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