scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

SPTPL: A NEW PULSED LATCH TYPE FLIP-FLOP IN HIGH-PERFORMANCE SYSTEM-ON-A-CHIP (SoC)

2007 ◽  
Vol 16 (02) ◽  
pp. 169-179 ◽  
Author(s):  
INHWA JUNG ◽  
MOO-YOUNG KIM ◽  
CHULWOO KIM
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Clock Frequency ◽  
Flip Flop ◽  
Reduce Power Consumption ◽  
Look Ahead ◽  
Clock Distribution Network ◽  
Double Edge ◽  
Pipeline Design ◽  
Circuit Technique

In many VLSI chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Traditionally, two approaches have been used: (1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; (2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. Recently, pulsed latch type flip-flops are introduced in several high-performance microprocessors to reduce E × D. In this paper, these flip-flops are described with their pros and cons. Then, a new circuit technique is described along with simulation results. The proposed pulsed latch reduces E × D by 82.6% to 95.4% compared to conventional flip-flops.

scholarly journals AREA AND POWER OPTIMIZED D-FLIP FLOP AND SUBTRACTOR

2021 ◽  
Vol 9 (1) ◽  
pp. 159-163
Author(s):  
T. Subhashini, M. Kamaraju, K. Babulu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Modern Technology ◽  
Power Reduction ◽  
Flip Flop ◽  
Xor Gate ◽  
Long Run

Low power is essential in today’s technology. It is most significant with high speed, small size and stability. So, power reduction is most important in modern technology using VLSI design techniques. Today most of the market necessities require low power, long run time and market which also deserve small size and high speed. In this paper several logic circuits DFF with 5 transistors and sub tractor circuit using powerless XOR gate and Groundless XNOR gates are implemented. In the proposed DFF, the area can be decreased by 62% & substarctor circuit, area decreased by 80% and power consumption of DFF and subtractor circuit are 15.4µW and 13.76µW respectively, but these are very less as compared to existing techniques.  

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals Low power design of ultra wideband PLL using 90 nm CMOS technology

2020 ◽  
Vol 20 (2) ◽  
pp. 727
Author(s):  
Fadhilah Binti Noor Al Amin ◽  
Nabihah Ahmad ◽  
Siti Hawa Ruslan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Vlsi Design ◽  
Electronic System ◽  
Low Power Design ◽  
Cmos Technology ◽  
Ultra Wideband

<span>The rapid growth of the electronic system has become one of the challenges in the high performance of Very Large Scale Integration (VLSI) design and has contributed to the evolution of Phase Locked Loop (PLL) system design as one of the inevitable and significant necessities in the modern days. This design focus on the development of PLL system that can operate at a high performance within the Ultra-Wideband (UWB) frequency but consume low power that may be useful for future device implementation in the communication system. All proposed sub modules of PLL is highly suitable for low power and high speed application as each of them consumes overall power consumption around 2 µW until 1 mW with frequency from 3.1 GHz to 10.6 GHz. All the design architecture, schematic, simulation and analysis are implemented using Synopsys Tool in 90 nm CMOS technology. Through the overall analysis, it can be concluded that this proposed sub modules design of the PLL system has better performance compared to previous work in terms of power consumption and frequency.</span>

A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics

2018 ◽  
Vol 27 (13) ◽  
pp. 1850205 ◽  
Author(s):  
Ramin Rajaei
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Radiation Effects ◽  
Large Scale ◽  
Vlsi Design ◽  
Magnetic Tunnel Junction ◽  
Cmos Technology ◽  
Flip Flop ◽  
Reliability Challenge

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

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