scholarly journals Dominance of the Digital (1990–2016)

2019 ◽  
Vol 13 (1) ◽  
pp. 106-109
Author(s):  
Thomas J. Misa
Keyword(s):  
Social Constructivism ◽  
Integrated Circuit ◽  
Internet Technology ◽  
Technological Determinism ◽  
Global Culture ◽  
Moore’S Law ◽  
Moore's Law ◽  
Technology And Culture ◽  
Firm Cooperation

Abstract This talk presents the theme that anchors the new third edition of Leonardo to the Internet: Technology and Culture from the Renaissance to the Present, which is organized around technical-economic-political “eras” spotlighting the long-term interactions of technology and culture. The book’s first edition (2004) concluded with an optimistic assessment of global culture, then added a pessimistic assessment of systemic risk (2011). The eras point to socio-economic structures that foster and channel the development of certain technologies (and not others). This approach steers for a middle ground between social constructivism and technological determinism. This talk analyzes Moore’s Law (1975–2005), widely hailed to explain, well, everything. By 1975 Gordon Moore appeared to accurately “predict” the doubling every 18 months of the number components on each integrated circuit. During these years chips expanded from roughly 2,000 to 600 million transistors; more important the “law” guided a technical revolution and an industry transformation. At first national and then international cooperative “roadmapping” exercises predicted the exact dimensions of chips in the future, and semiconductor companies all aimed exactly where their peers were aiming. So Moore’s Law is a self-fulfilling prophecy supported for three decades by inter-firm cooperation and synchronized R&D.

Photolithography Alignment Mark Transfer System for Low Cost, Advanced Packaging, and Bonded Wafer Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001302-001327 ◽  
Author(s):  
Tom Swarbrick ◽  
Keith Best ◽  
Casey Donaher ◽  
Steve Gardner
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Final Analysis ◽  
System Throughput ◽  
Latent Image ◽  
Moore’S Law ◽  
Moore's Law ◽  
Advanced Packaging ◽  
Alignment Mark

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm has presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. And in the very cost sensitive advanced packaging arena, Outsourced Semiconductor Assembly and Test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from the backend processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, where the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with Infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist is then stripped and cleaned. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2um is readily achievable, with no impact on system throughput.

scholarly journals Ultra-precision engineering in lithographic exposure equipment for the semiconductor industry

2012 ◽  
Vol 370 (1973) ◽  
pp. 3950-3972 ◽  
Author(s):  
Robert-H. Munnig Schmidt
Keyword(s):  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Atomic Scale ◽  
Precision Engineering ◽  
Exposure System ◽  
Moore’S Law ◽  
Moore's Law ◽  
Positioning Systems ◽  
Motion System ◽  
The Future

The developments in lithographic tools for the production of an integrated circuit (IC) are ruled by ‘Moore’s Law’: the density of components on an IC doubles in about every two years . The corresponding size reduction of the smallest detail in an IC entails several technological breakthroughs. The wafer scanner, the exposure system that defines those details, is the determining factor in these developments. This review deals with those aspects of the positioning systems inside these wafer scanners that enable the extension of Moore’s Law into the future. The design of these systems is increasingly difficult because of the accuracy levels in the sub-nanometre range coupled with motion velocities of several metres per second. In addition to the use of feedback control for the reduction of errors, high-precision model-based feed-forward control is required with an almost ideally reproducible motion-system behaviour and a strict limitation of random disturbing events. The full mastering of this behaviour even includes material drift on an atomic scale and is decisive for the future success of these machines.

PHOTOLITHOGRAPHY ALIGNMENT MARK TRANSFER SYSTEM FOR LOW COST ADVANCED PACKAGING AND BONDED WAFER APPLICATIONS

2016 ◽  
Vol 2016 (1) ◽  
pp. 000315-000320 ◽  
Author(s):  
Keith Best ◽  
Steve Gardner ◽  
Casey Donaher
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Final Analysis ◽  
System Throughput ◽  
Latent Image ◽  
Moore’S Law ◽  
Moore's Law ◽  
Advanced Packaging ◽  
Alignment Mark

Abstract Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm have presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. In this very cost sensitive advanced packaging arena, outsourced semiconductor assembly and test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from back-end processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, that the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist stripped, and the lithography layer reworked. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper-based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2μm is readily achievable, with no impact on system throughput.

The Consumption of Technology in Everyday Life: Car, Telephone, and Television in Sweden and America in Comparative-Historical Perspective

2002 ◽  
Vol 7 (4) ◽  
pp. 45-59 ◽  
Author(s):  
Ralph Schroeder
Keyword(s):  
Everyday Life ◽  
Historical Perspective ◽  
Small Towns ◽  
Social Constructivist ◽  
Technological Determinism ◽  
Technology And Culture ◽  
Social Shaping

This essay examines the consumption of technology in everyday life by considering three major technologies - car, telephone, and television. The argument attempts to go beyond technological determinism, which is typically not grounded in the study of everyday life, as well as beyond social shaping/social constructivist views that are tied to particular times and places, and thus unable to recognize broader and more long-term patterns of change. To make this argument, Sweden and America, two countries for which detailed evidence is available for different periods of time, including several studies of ‘typical’ small towns, are compared in historical perspective. In addition to synthesizing this evidence, the essay draws on neo-functionalist and Weberian ideas about technology and culture to argue that there is an overall pattern whereby the consumption of technology in everyday life simultaneously homogenizes leisure and sociable activities and at the same time makes them more diverse.

scholarly journals Moore's Law: A Review of Feature Size Shrinkage and its Effect on Microscopy in the Semiconductor Industry

2007 ◽  
Vol 15 (3) ◽  
pp. 6-11
Author(s):  
John Mardinly
Keyword(s):  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Feature Size ◽  
Moore’S Law ◽  
Moore's Law ◽  
Number Of Components ◽  
Device Scaling ◽  
Microscopy Techniques

SummaryIn 1965, Gordon Moore predicted that the number of components in an integrated circuit would double every year. The drive for higher performance with greater economy has been a major factor in the pursuit of Moore's Law. Device scaling is expected to continue without interruption, and products manufactured using a nominal 22nm feature size should become commercially available by the year 2011. This article will detail the technology enablers that make Moore's Law possible, and the improvements in microscopy techniques required to meet the challenges that Moore's Law presents.

scholarly journals Evolutionary Model of Moore’s Law

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Joachim Kaldasch
Keyword(s):  
Production Technology ◽  
Evolutionary Model ◽  
New Production ◽  
Preferential Growth ◽  
Moore’S Law ◽  
Moore's Law ◽  
Size Evolution ◽  
Wafer Size ◽  
Physical Boundary

Moore suggested an exponential growth of the number of transistors in integrated electronic circuits. In this paper, Moore’s law is derived from a preferential growth model of successive production technology generations. The theory suggests that products manufactured with a new production technology generating lower costs per unit have a competitive advantage on the market. Therefore, previous technology generations are replaced according to a Fisher-Pry law. Discussed is the case that a production technology is governed by a cost relevant characteristic. If this characteristic is bounded by a technological or physical boundary, the presented evolutionary model predicts an asymptotic approach to this limit. The model discusses the wafer size evolution and the long term evolution of Moore’s law for the case of a physical boundary of the lithographic production technology. It predicts that the miniaturization process of electronic devices will slow down considerably in the next two decades.

The Tortoise and the Hare? Due Process and Unconstitutionally Obtained Evidence in the Digital Age

2018 ◽  
Vol 18 (3) ◽  
pp. 169-170
Author(s):  
Róisín Costello
Keyword(s):  
Integrated Circuit ◽  
Due Process ◽  
Digital Age ◽  
Personal Computers ◽  
Rapid Rate ◽  
Moore’S Law ◽  
Moore's Law

Under Moore's Law the number of transistors in an integrated circuit doubles relative to cost and size every two years. In practical terms this means personal computers become twice as powerful and half as large every 24 months. However, this rapid rate of proliferation and improvement has not been mirrored in law.

Chips with Everything

2017 ◽  
Author(s):  
David Segal
Keyword(s):  
Quantum Computing ◽  
Integrated Circuits ◽  
Critical Role ◽  
Moore’S Law ◽  
Moore's Law ◽  
Silicon Chips ◽  
History Of ◽  
Future Potential ◽  
Digital Computers ◽  
Dna Computer

Chapter 3 highlights the critical role materials have in the development of digital computers. It traces developments from the cat’s whisker to valves through to relays and transistors. Accounts are given for transistors and the manufacture of integrated circuits (silicon chips) by use of photolithography. Future potential computing techniques, namely quantum computing and the DNA computer, are covered. The history of computability and Moore’s Law are discussed.

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