scholarly journals Uncertainty of S-Parameter Measurements on PCBs due to Imperfections in the TRL Line Standard

2021 ◽  
Vol 21 (5) ◽  
pp. 369-378
Author(s):  
Hyunji Koo ◽  
Martin Salter ◽  
No-Weon Kang ◽  
Nick Ridler ◽  
Young-Pyo Hong

This paper evaluates the uncertainty of S-parameter measurements on multilayer printed circuit boards (PCBs) due to the uncertainties of the dimensions and dielectric properties of the line standard in the Thru-Reflect-Line (TRL) calibration. This evaluation is performed in two ways: one is based on repeated TRL calibrations with a randomly perturbed line standard, and the other is based on equations given by Stumper. The two methods require the uncertainties of the S-parameters of the TRL line standard, which are obtained from the uncertainties of the dimensions and dielectric properties using three-dimensional electromagnetic Monte Carlo simulation. The two methods agree well with each other. This study also shows how to apply impedance renormalization in Stumper’s equations. We design the TRL standards and the devices under test (DUTs) in PCB stripline and precisely measure the cross-sectional dimensions of the fabricated striplines. Uncertainty analysis based on the measured values enables us to investigate the impact of realistic deviations in the dimensions of the TRL line standard on the S-parameter measurement uncertainty of the DUTs. Finally, as an example, we evaluated the uncertainty in the measured S-parameters of a Beatty line on the fabricated PCB.

Materials ◽  
2021 ◽  
Vol 14 (18) ◽  
pp. 5186
Author(s):  
Szabolcs Fogarasi ◽  
Árpád Imre-Lucaci ◽  
Florica Imre-Lucaci

The study was carried out with the aim to demonstrate the applicability of a combined chemical–electrochemical process for the dismantling of waste printed circuit boards (WPCBs) created from different types of electronic equipment. The concept implies a simple and less polluting process that allows the chemical dismantling of WPCBs with the simultaneous recovery of copper from the leaching solution and the regeneration of the leaching agent. In order to assess the performance of the dismantling process, various tests were performed on different types of WPCBs using the 0.3 M FeCl3 in 0.5 M HCl leaching system. The experimental results show that, through the leaching process, the electronic components (EC) together with other fractions can be efficiently dismounted from the surface of WPCBs, with the parallel electrowinning of copper from the copper rich leaching solution. In addition, the process was scaled up for the dismantling of 100 kg/h WPCBs and modeled and simulated using process flow modelling software ChemCAD in order to assess the impact of all steps and equipment on the technical and environmental performance of the overall process. According to the results, the dismantling of 1 kg of WPCBs requires a total energy of 0.48 kWh, and the process can be performed with an overall low environmental impact based on the obtained general environmental indexes (GEIs) values.


2019 ◽  
Vol 2019 (1) ◽  
pp. 000492-000502 ◽  
Author(s):  
T. Bernhard ◽  
L. Gregoriades ◽  
S. Branagan ◽  
L. Stamp ◽  
E. Steinhäuser ◽  
...  

Abstract A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.


Minerals ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 79 ◽  
Author(s):  
Linlin Tong ◽  
Qianfei Zhao ◽  
Ali Kamali ◽  
Wolfgang Sand ◽  
Hongying Yang

The efficient extraction of copper as a valuable metal from waste printed circuit boards (WPCBs) is currently attracting growing interest. Here, we systematically investigated the impact of bacteria on the efficiency of copper leaching from WPCBs, and evaluated the effect of graphite on bioleaching performance. The HQ0211 bacteria culture containing Acidithiobacillus ferrooxidans, Ferroplasma acidiphilum, and Leptospirillum ferriphilum enhanced Cu-leaching performance in either ferric sulfate and sulfuric acid leaching, so a final leaching of up to 76.2% was recorded after 5 days. With the addition of graphite, the percentage of copper leaching could be increased to 80.5%. Single-factor experiments confirmed the compatibility of graphite with the HQ0211 culture, and identified the optimal pulp density of WPCBs, the initial pH, and the graphite content to be 2% (w/v), 1.6, and 2.5 g/L, respectively.


Author(s):  
Erik Jung ◽  
Dirk Wojakowski ◽  
Alexander Neumann ◽  
Rolf Aschenbrenner ◽  
Herbert Reichl

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. To further the miniaturization of future products the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP) is a promising approach. Here, use of recent manufacturing methods allows to merge the SiP concept with a volumetric integration of IC’s. Up to now, most of the systems make use of single- or double-sided populated system carriers. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB’s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. Results on FEM simulations and technical achievements are presented.


2014 ◽  
Vol 56 (6) ◽  
pp. 1559-1566 ◽  
Author(s):  
Marina Y. Koledintseva ◽  
Aleksei V. Rakov ◽  
Alexei I. Koledintsev ◽  
James L. Drewniak ◽  
Scott Hinaga

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