scholarly journals Negative High Voltage DC-DC Converter Using a New Cross-Coupled Structure

2015 ◽  
Vol 10 (3) ◽  
pp. 158-165
Author(s):  
Jun Zhao ◽  
Kyung Ki Kim ◽  
Yong-Bin Kim
Keyword(s):  
High Voltage ◽  
Power Supply ◽  
Power Efficiency ◽  
Current Problem ◽  
Negative Charge ◽  
Supply Voltage ◽  
Charge Pump ◽  
Complete Analysis ◽  
Voltage Gain ◽  
Variable Voltage

In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.

scholarly journals T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 507
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Arash Hejazi ◽  
Joon-Mo Yoo ◽  
...  
Keyword(s):  
Negative Charge ◽  
Switching Time ◽  
Supply Voltage ◽  
Charge Pump ◽  
Design Rule ◽  
Absolute Maximum ◽  
Optimum Number ◽  
Rf Switch ◽  
Voltage Range ◽  
Custom Made

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.

scholarly journals Performance enhancement analysis of an isolated DC-DC converter using fuzzy logic controller

2017 ◽  
Vol 7 (1.2) ◽  
pp. 186 ◽  
Author(s):  
S. Muthu Balaji ◽  
R. Anand ◽  
P. Senthil Pandian
Keyword(s):  
Fuzzy Logic ◽  
High Voltage ◽  
Output Voltage ◽  
Fuzzy Logic Controller ◽  
Performance Enhancement ◽  
Supply Voltage ◽  
Boost Converter ◽  
Open Loop ◽  
Voltage Gain ◽  
Power Application

High voltage gain dc-dc converters plays an major role in many modern industrialized applications like PV and fuel cells, electrical vehicles, dc backup systems (UPS, inverter), HID (high intensity discharge) lamps. As usual boost converter experiences a drawback of obtaining a high voltage at maximum duty cycle. Hence in order to increase the voltage gain of boost converter, this paper discusses about the advanced boost converter using solar power application. By using this technique, boost converter attains a high voltage which is ten times greater than the input supply voltage. The output voltage can be further increased to more than ten times the supply voltage by using a parallel capacitor and a coupled inductor. The voltage stress across the switch can be reduced due to high output voltage. The Converter is initially operated in open loop and then it is connected with closed loop. More over the fuzzy logic controller is used for the ripple reduction.

scholarly journals Negative charge pump circuit with large output current and high power efficiency

2009 ◽  
Vol 6 (6) ◽  
pp. 304-309 ◽  
Author(s):  
Ji-Hye Bong ◽  
Yong-Jin Kwon ◽  
Daejeong Kim ◽  
Kyeong-Sik Min
Keyword(s):  
High Power ◽  
Power Efficiency ◽  
Negative Charge ◽  
Charge Pump ◽  
Output Current ◽  
Charge Pump Circuit ◽  
High Power Efficiency ◽  
Large Output

scholarly journals A high-efficiency and compact charge pump with charge recycling scheme and finger boost capacitor

2019 ◽  
Vol 292 ◽  
pp. 01020
Author(s):  
Hui Peng ◽  
Pieter Bauwens ◽  
Herbert De Pauw ◽  
Jan Doutreloigne
Keyword(s):  
Power Supply ◽  
Power Efficiency ◽  
Output Voltage ◽  
High Efficiency ◽  
Charge Pump ◽  
Parasitic Capacitance ◽  
Chip Area ◽  
Charge Recycling ◽  
Compact Charge

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. The proposed four-stage charge pump with finger capacitor can achieve 14.2 V output voltage from a 3 V power supply. The finger capacitor can increase the power efficiency of the charge pump to 60.5% and save chip area as well.

scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

scholarly journals Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications

2021 ◽  
Vol 27 (2) ◽  
pp. 31-39
Author(s):  
Jakob K. Toft ◽  
Ivan H. H. Jorgensen
Keyword(s):  
Power Consumption ◽  
Mechanical System ◽  
High Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Micro Electro Mechanical System ◽  
Silicon On Insulator ◽  
High Bias ◽  
Low Supply Voltage ◽  
Very High

This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm silicon-on-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.

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