scholarly journals Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications

2021 ◽  
Vol 27 (2) ◽  
pp. 31-39
Author(s):  
Jakob K. Toft ◽  
Ivan H. H. Jorgensen
Keyword(s):  
Power Consumption ◽  
Mechanical System ◽  
High Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Micro Electro Mechanical System ◽  
Silicon On Insulator ◽  
High Bias ◽  
Low Supply Voltage ◽  
Very High

This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm silicon-on-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.

scholarly journals A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

2021 ◽  
Author(s):  
Jakob K. Toft ◽  
Ivan H. H. Jorgensen
Keyword(s):  
High Voltage ◽  
Rise Time ◽  
Output Voltage ◽  
Supply Voltage ◽  
State Of The Art ◽  
Charge Pump ◽  
Micro Electro Mechanical System ◽  
Charge Pumps ◽  
Capacitive Load ◽  
Very High

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

scholarly journals A Single-Chip High-Voltage Integrated Actuator for Biomedical Ultrasound Scanners

Sensors ◽  
2019 ◽  
Vol 19 (23) ◽  
pp. 5063 ◽  
Author(s):  
Hsia ◽  
Hsiao ◽  
Huang
Keyword(s):  
Power Consumption ◽  
High Voltage ◽  
High Speed ◽  
Low Voltage ◽  
Second Harmonic ◽  
Pulse Signal ◽  
Silicon On Insulator ◽  
Imaging Systems ◽  
Output Stage ◽  
Static Power

This article presents a high-voltage (HV) pulse driver based on silicon-on-insulator (SOI) technology for biomedical ultrasound actuators and multi-channel portable imaging systems specifically. The pulse driver, which receives an external low-voltage drive signal and produces high-voltage pulses with a balanced rising and falling edge, is designed by synthesizing high-speed, capacitor-coupled level-shifters with a high-voltage H-bridge output stage. In addition, an on-chip floating power supply has also been developed to simplify powering the entire system and reduce static power consumption. The electrical and acoustic performance of the integrated eight-channel pulse driver has been verified by using medical-grade ultrasound probes to acquire the transmit/echo signals. The driver can produce pulse signals >100 Vpp with rise and fall times within 18.6 and 18.5 ns, respectively. The static power required to support the overall system is less than 3.6 mW, and the power consumption of the system during excitation is less than 50 mW per channel. The second harmonic distortion of the output pulse signal is as low as −40 dBc, indicating that the integrated multi-channel pulse driver can be used in advanced portable ultrasonic imaging systems.

Application Research of MEMS ADXL345

2012 ◽  
Vol 457-458 ◽  
pp. 1550-1553 ◽  
Author(s):  
Cun Shan Xu
Keyword(s):  
Power Consumption ◽  
Mechanical System ◽  
Lower Cost ◽  
Electronic Devices ◽  
Micro Electro Mechanical System ◽  
Dynamical Characteristic ◽  
Application Research ◽  
Proper Method

Due to excellent characteristics of lower cost, higher reliability, smaller power consumption, less volume and lighter weight, micro electro mechanical system (MEMS) has been widely accepted and used in portable electronic devices. Based on port S3C2440, a proper method is presented to carry out the study of dynamical characteristic for tri-axial digital accelerometer ADXL345. The results could provide a well approach for improvement of this novel component.

scholarly journals A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

2019 ◽  
Vol 9 (1) ◽  
pp. 8 ◽  
Author(s):  
Jean-Frédéric Christmann ◽  
Florent Berthier ◽  
David Coriat ◽  
Ivan Miro-Panades ◽  
Eric Guthmuller ◽  
...  
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Silicon On Insulator ◽  
Instruction Set ◽  
Voltage Level ◽  
Fully Depleted ◽  
Environmental Variations ◽  
Reduced Instruction Set Computer ◽  
Low Activity ◽  
28 Nm

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.

scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

scholarly journals Robust 12T Sram Cell Using 45nm Technology

2020 ◽  
pp. 170-174
Author(s):  
N. Geetha Rani ◽  
N. Jyothi ◽  
P. Leelavathi ◽  
P. Deepthi Swarupa Rani ◽  
S. Reshma
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Sram Cell ◽  
Static Power ◽  
Low Supply Voltage ◽  
Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

scholarly journals Negative High Voltage DC-DC Converter Using a New Cross-Coupled Structure

2015 ◽  
Vol 10 (3) ◽  
pp. 158-165
Author(s):  
Jun Zhao ◽  
Kyung Ki Kim ◽  
Yong-Bin Kim
Keyword(s):  
High Voltage ◽  
Power Supply ◽  
Power Efficiency ◽  
Current Problem ◽  
Negative Charge ◽  
Supply Voltage ◽  
Charge Pump ◽  
Complete Analysis ◽  
Voltage Gain ◽  
Variable Voltage

In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.

scholarly journals An Analog Interface Circuit for Capacitive Angle Encoder Based on a Capacitance Elimination Array and Synchronous Switch Demodulation Method

Sensors ◽  
2019 ◽  
Vol 19 (14) ◽  
pp. 3116 ◽  
Author(s):  
Bo Hou ◽  
Bin Zhou ◽  
Xiang Li ◽  
Zhenyi Gao ◽  
Qi Wei ◽  
...  
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Interface Circuit ◽  
Machine Systems ◽  
Sensitive Structure ◽  
Angle Encoder ◽  
Low Supply Voltage ◽  
Control Machine

This paper presents an analog interface application-specific integrated circuit (ASIC) for a capacitive angle encoder, which is widely used in control machine systems. The encoder consists of two parts: a sensitive structure and analog readout circuit. To realize miniaturization, low power consumption, and easy integration, an analog interface circuit including a DC capacitance elimination array and switch synchronous demodulation module was designed. The DC capacitance elimination array allows the measurement circuit to achieve a very high capacitance to voltage conversion ratio at a low supply voltage. Further, the switch synchronous demodulation module effectively removes the carrier signal and greatly reduces the sampling rate requirement of the analog-to-digital converter (ADC). The ASIC was designed and fabricated with standard 0.18 µm CMOS processing technology and integrated with the sensitive structure. An experiment was conducted to test and characterize the performance of the proposed analog interface circuit. The encoder measurement results showed a resolution of 0.01°, power consumption of 20 mW, and accuracy over the full absolute range of 0.1°, which indicates the great potential of the encoder for application in control machine systems.

Sign in / Sign up

Export Citation Format

Share Document