Extended Circuit Edit, Analysis and Trimming Capabilities Based on the Backside Focused Ion Beam Created Ultra Thin Silicon Platform

2009 ◽  
Author(s):  
Rudolf Schlangen ◽  
Rainer Leihkauf ◽  
Uwe Kerst ◽  
Christian Boit ◽  
Peter Egger ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Device Performance ◽  
Integrated Circuit Design ◽  
Analysis Techniques ◽  
Design Changes ◽  
Almost All ◽  
Critical Regions

Abstract Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.

Direct Imaging of Device Characteristics In a Focused ion Beam System

1998 ◽  
Vol 4 (S2) ◽  
pp. 652-653 ◽  
Author(s):  
A. N. Campbell ◽  
J. M. Soden
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Material Removal ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Yield Enhancement ◽  
The Past ◽  
Design Changes ◽  
Design Debugging

A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

scholarly journals Die Backside FIB Preparation for Identification and Characterization of Metal Voids

1999 ◽  
Author(s):  
Ann N. Campbell ◽  
William F. Filter ◽  
Nicholas Antoniou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Milling Process ◽  
Plan View ◽  
Metal Interconnects

Abstract Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

Studies of Buried Voids Capturing with e-Beam Inspection System and Confirmation with Physical Failure Analysis

2012 ◽  
Author(s):  
Hong Xiao ◽  
Ximan Jiang
Keyword(s):  
Electron Beam ◽  
Electron Microscope ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Energetic Electron ◽  
Optical Microscope ◽  
Inspection System ◽  
Dual Beam

Abstract In this paper, a novel inspection mode of electron beam inspection (EBI) that can effectively detect buried voids in tungsten (W) plugs is reported for the first time. Buried voids in metal are a defect of interest (DOI) that cannot be captured by either optical inspection or traditional EBI modes. The detection of buried voids is achieved by using energetic electron beam (e-beam) with energy high enough to penetrate into metal and reach the buried void. By selecting desired secondary electrons to form the inspection images, strong contrast between the defective tungsten plugs and normal ones can be achieved. Failure analysis was performed on the DOI that is unique to this new EBI mode. After optical microscope locating and laser marking, we successfully recaptured DOI with scanning electron microscope (SEM) and capped the DOI with e-beam assisted platinum (Pt) deposition. Later a dual-beam focused ion beam (FIB) system was used to re-locate the Pt-capped DOI and prepare samples for transmission electron microscope (TEM). TEM images confirmed the unique DOI were buried voids in the metal plugs, which could affect resistance of interconnect in integrated circuit (IC) chip and impact the IC yield.

Site Specific 2-D Implant Profiling Using FIB Assisted SCM

2002 ◽  
Author(s):  
Konrad Jarausch ◽  
John F. Richards ◽  
Lloyd Denney ◽  
Alex Guichard ◽  
Phillip E. Russell
Keyword(s):  
Electron Microscopy ◽  
Failure Analysis ◽  
Cross Sections ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Two Dimensional ◽  
Semiconductor Technology ◽  
Site Specific ◽  
Analysis Techniques ◽  
Profiling Techniques

Abstract Advances in semiconductor technology are driving the need for new metrology and failure analysis techniques. Failures due to missing, or misregistered implants are particularly difficult to resolve. Two-dimensional implant profiling techniques such as scanning capacitance microscopy (SCM) rely on polish preparation, which makes reliably targeting sub 0.25 um structures nearly impossible.[1] Focused ion beam (FIB) machining is routinely used to prepare site-specific cross-sections for electron microscopy inspection; however, FIB induced artifacts such as surface amorphization and Ga ion implantation render the surface incompatible with SCM (and selective etching techniques). This work describes a novel combination of FIB machining and polish preparation that allows for site-specific implant profiling using SCM.

Voltage Contrast Application on 1M SRAM Single Bit Failure Analysis

1997 ◽  
Author(s):  
D. Luo ◽  
X. Song
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Access Memory ◽  
Operating Life ◽  
New Techniques ◽  
Analysis Techniques ◽  
Temperature Operating ◽  
Voltage Contrast

Abstract A single bit failure is the most common and the most difficult failure mode to analyze in a Static Random Access Memory (SRAM). As chip feature sizes decrease, the difficulties compound. Traditional failure analysis techniques are often ineffective, particularly for high temperature operating life (HTOL) failures, because HTOL failures are most often caused by subtle physical defects. A new analysis approach, using Focused Ion Beam (FIB) cross-sectioning combined with Fffi passive voltage contrast (PVC), greatly enhances the analysis success rate. In this paper, we outline the use of these new techniques and apply them to a technologically important problem.

Novel Approach of Improving Secondary Electron Detector in FIB System

2018 ◽  
Author(s):  
Steve Wang ◽  
Jim McGinn ◽  
Peter Tvarozek ◽  
Amir Weiss
Keyword(s):  
Integrated Circuit ◽  
Secondary Electron ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Vital Role ◽  
Electron Detector ◽  
System A ◽  
Novel Approach

Abstract Secondary electron detector (SED) plays a vital role in a focused ion beam (FIB) system. A successful circuit edit requires a good effective detector. Novel approach is presented in this paper to improve the performance of such a detector, making circuit altering for the most advanced integrated circuit (IC) possible.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

TEM Sample Preparation Tricks for Advanced DRAMs

2015 ◽  
Author(s):  
Ching Shan Sung ◽  
Hsiu Ting Lee ◽  
Jian Shing Luo
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Sample Preparation ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Tem Analysis ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Characterization Of Materials

Abstract Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

2000 ◽  
Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Front Side ◽  
Automatic Determination ◽  
Metal Line ◽  
New Approach ◽  
Metal Layers

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM

2013 ◽  
Author(s):  
Max L. Lifson ◽  
Carla M. Chapman ◽  
D. Philip Pokrinchak ◽  
Phyllis J. Campbell ◽  
Greg S. Chrisman ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Germanium ◽  
Focused Ion Beam ◽  
Surface Defects ◽  
Ion Beam ◽  
Misfit Dislocations ◽  
Tem Analysis ◽  
Plan View ◽  
Near Surface ◽  
Straightforward Method

Abstract Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

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