Complementary Optical Techniques for Advanced IC Failure Analysis – Case Study

Author(s):  
Joy Y. Liao ◽  
Howard Lee Marks ◽  
Herve Deslandes

Abstract We investigated and demonstrated the advantages and limitations of several optical methodologies as valuable silicon failure analysis techniques, and how they could be used in a complementary manner to assist in shortening the diagnostic time.

Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.


Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.


Author(s):  
D. Davis ◽  
O. Diaz de Leon ◽  
L. Hughes ◽  
S. V. Pabbisetty ◽  
R. Parker ◽  
...  

Abstract The advent of Flip Chip and other complex package configurations and process technologies have made conventional failure analysis techniques inapplicable. This paper covers the ways in which conventional techniques have been modified to meet the FA challenges presented by these new devices – specifically, by forcing analysis to be done from the backside of the device. Modifications to the traditional FA process steps, including new sample preparation methods, changes in hardware, and alterations to physical failure analysis processes are described. To demonstrate the use of backside analytical approaches, some examples of applications and a case study are also included.


Author(s):  
Timothy C. Wilkins

Abstract This paper describes the organization, process, and challenges of an international network of electrical and mechanical failure analysis labs that leverage lessons learned, resources, failure analysis techniques, and benchmarking of current common problems. Formed 11 years ago as just an electrical/electronic part failure analysis council within Otis Elevator and Carrier, this group has grown to be a network of 16 electrical and 22 mechanical labs. This council is a one of a kind network that also includes suppliers of parts to UTC. This paper will also illustrate the advantages of cross-functional and divisional leveraging with case study examples.


Author(s):  
Jose Z. Garcia ◽  
Kris Dickson

Abstract This paper describes how a DDR loopback test failure was analyzed successfully after being repackaged from an MBGA into a TBGA package substrate. DDR loopback test methodology is discussed as well as the advanced failure analysis techniques that were used to identify the root cause of failure.


2014 ◽  
Vol 891-892 ◽  
pp. 1041-1046
Author(s):  
Trevor M. Leacy ◽  
Roberto Ojeda

Marine grade alloys are extensively being used in high speed vessels such as patrol crafts, ferries and crew boats, where a reduction of the structural weight is critical to achieve higher speeds [1]. The use of aluminium has forced marine industry engineers to develop methods to design against fatigue failure. This has largely been addressed by the development of design standards, analysis techniques and the improvement of quality control and construction methods [2]. Nevertheless, even with these advancements there is a continued need for the development and improvement of aluminium analysis methods and guidelines [3].


Author(s):  
Erick Kim ◽  
Kamjou Mansour ◽  
Gil Garteiz ◽  
Javeck Verdugo ◽  
Ryan Ross ◽  
...  

Abstract This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.


Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.


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