Subsurface Imaging of Multi-Level Integrated Circuits Using Scanning Electron Acoustic Microscopy

Author(s):  
L. Meng ◽  
J.C.H. Phang ◽  
A.G. Street

Abstract The capability of the Scanning Electron Acoustic Microscopy (SEAM) technique for high resolution non-destructive subsurface imaging at different depths for a multi-level integrated circuit is assessed. Experimental results using a beveled DRAM IC sample are used to quantify the effect of the electron beam energy and modulation frequency on contrast, spatial resolution and depth of focus of SEAM amplitude and phase images.

Author(s):  
S. Khadpe ◽  
R. Faryniak

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.


Author(s):  
Alexander Sorkin ◽  
Chris Pawlowicz ◽  
Alex Krechmer ◽  
Michael W. Phaneuf

Abstract Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.


1996 ◽  
Vol 445 ◽  
Author(s):  
Nickolaos Strifas ◽  
Aris Christou

AbstractThe reliability of plastic packaged integrated circuits was assessed from the point of view of interfacial mechanical integrity. It is shown that the effect of structural weaknesses caused by poor bonding, voids, microcracks or delamination may not be evident in the electrical performance characteristics, but may cause premature failure. Acoustic microscopy (C-SAM) was selected for nondestructive failure analysis of the plastic integrated circuit (IC) packages. Integrated circuits in plastic dual in line packages were initially subjected to temperature (25 °C to 85 °C) and humidity cycling (50 to 85 %) where each cycle was of one hour duration and for over 100 cycles and then analyzed. Delamination at the interfaces between the different materials within the package, which is a major cause of moisture ingress and subsequent premature package failure, was measured. The principal areas of delamination were found along the leads extending from the chip to the edge of the molded body and along the die surface itself. Images of the 3-D internal structure were produced that were used to determine the mechanism for a package failure. The evidence of corrosion and stress corrosion cracks in the regions of delamination was identified.


1996 ◽  
Vol 99 (11) ◽  
pp. 853-857 ◽  
Author(s):  
Shuwei Li ◽  
Fuming Jiang ◽  
Qingrui Yin ◽  
Yixin Jin

2001 ◽  
Vol 7 (S2) ◽  
pp. 484-485
Author(s):  
Ling Xiao ◽  
Zhuguan Liang ◽  
Yawen Li ◽  
Jian Wang ◽  
Kailin Zhou ◽  
...  

In the paper, we firstly publish a new method of internal micrographic visualization of semiconductor and IC. The quality and reliability of the semiconductor materials (SM) and the integrated circuits (IC) have always been concerned Having a high resolution, high reliable and nondestructive detection method is the key element for their improvements.Silicon oxide layers are used to provide the electrical insulation in the multi-structured ICs. The IC device surfaces are often protected by silicon oxide and silicon nitride layers. Therefore, these insulation layers also cover any inhomogeneity and defect located within the IC devices. It is necessary to have an examining method to detect those defects that are under the insulation layers without damaging the samples. However, the conventional scanning electron microscope (SEM) cannot be utilized to image and examine the surfaces that are positioned below the insulation layers.Novel nondestructive and contactless method has been developed in our laboratory to obtain the internal micrograph that crosses the surface of the semiconductor material and the integrated circuit.


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