High Resolution Localization Using Lock-in Based Electron Beam Methods

Author(s):  
Felix Rolf ◽  
Christian Hollerith ◽  
Christian Feuerbaum

Abstract With decreasing transistor sizes accurate failure localization becomes more and more important in order to find the root cause of failures with high efficiency. Field returns are a special challenge, since there is usually only one sample for preparation. Hence, reliable high resolution localization is mandatory for a successful preparation. Optical beam induced resistance change (OBIRCH) is a powerful tool for localization but has resolution limitations due to the diameter of the optical beam. The tool can be further improved by the lock-in technique. In this paper we demonstrate that the lock-in technique can also be applied for electron beam localization methods like electron beam induced current (EBIC) / electron beam absorbed current (EBAC) and resistance change imaging (RCI) / electron beam induced resistance change (EBIRCH).

Author(s):  
Brett A. Buchea ◽  
Christopher S. Butler ◽  
H.J. Ryu ◽  
Wen-hsien Chuang ◽  
Martin von Haartman ◽  
...  

Abstract A novel fault isolation technique, electron beam induced resistance change (EBIRCh), allows for the direct stimulation and localization of eBeam current sensitive defects with resolution of approximately 100nm square, continuing a history of beam based failure isolation methods. EBIRCh has been shown to work over a range of defects, significantly decreasing the time required for isolation of shorts through straightforward high resolution imagery, allowing for explicit visual defect isolation with a linear resolution of approximately 10nm. This paper discusses the operational setups for the source and amplifier while performing an EBIRCh scan, describes the processes involved in the Intel test vehicle that was used to test EBIRCh, and provides information on two independent functional theories for EBIRCh that operate in conjunction to a greater or lesser extent depending on the defect type. EBIRCh is expected to improve through-put and resolution on various defect types compared to conventional fault isolation techniques.


Author(s):  
Jim Douglass ◽  
Sohrab Pourmand

Abstract This paper shows that by combining electrical fault isolation and characterization by microprobing with physical fault isolation techniques both what is wrong with the circuit and where the defect is located can be determined with less microprobing and more safety from electrical recovery. In the first example, the unit was powered up using the optical beam induced resistance change (OBIRCH) supply, and OBIRCH was performed to determine if there were OBIRCH site differences between the good part and the return. The second example uses a combination of electrical fault isolation and characterization with microprobing and the physical fault isolation tool of lock in thermography (LIT). With these two examples, it has been shown that the use of electrical fault isolation and microprobing can be used to enhance the physical fault isolation tools of OBIRCH and LIT.


2011 ◽  
Vol 12 (10) ◽  
pp. 1632-1637 ◽  
Author(s):  
Heng-Tien Lin ◽  
Chang-Yu Lin ◽  
Zingway Pei ◽  
Jun-Rong Chen ◽  
Yi-Jen Chan ◽  
...  

Author(s):  
F. Altmann ◽  
C. Schmidt ◽  
J. Beyersdorfer ◽  
M. Simon-Najasek ◽  
C. Große ◽  
...  

Abstract In this paper different methods and novel tools for failure localisation and high resolution material analysis for open TSV interconnects will be discussed. The paper shows the application of enhanced methods for the localisation of sidewall shorts in open TSV structures by adapted Photoemission Microscopy (PEM), Lock-in Thermography (LIT) and Electron Beam Absorbed Imaging (EBAC). In addition, a new highly efficient target preparation technique is presented, which allows the combination of Laser and FIB milling, in order to access TSV sidewall defects. Finally the use of this technique is demonstrated in a failure analysis case study.


2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002160-002198
Author(s):  
Rudolf Schlangen ◽  
Herve Deslandes ◽  
Toru Toda ◽  
Toshinobu Nagatomo ◽  
Shigeki Sako ◽  
...  

Root cause analysis for package defects is currently performed by de-processing the package until such defects can be physically seen. However, many such defects within the package are removed, or are confused with defects created during de-processing itself. 3D X-ray has been used to analyze such physical defects within a packaged device in a non-destructive manner. However, the increasing density and associated shrinkage of components such as multi-layered substrates require significantly higher resolutions, which translates to longer times. High resolution X-ray is impractical when searching for a defect over a wide area due to the time to acquire detailed 3D images (~24 hrs). Thermal emission analysis has been widely used for localizing defects on ICs. Recent advancement in thermal emission camera technology coupled with lock-in thermography has allowed orders of magnitude better sensitivity ( < 1μW) and improvement in localization resolution (x,y to < 3 um). However, the application of lock-in thermography has been primarily limited to defect localization at the die level [1]. A a highly sensitive MWIR camera combined with a real time lock-in technique demonstrates the capability to localize defects within packaged devices, even through its mold compound. The technique accurately predicts the depth (z) of a thermal defect within the device (< + 5%) This paper will demonstrate multiple examples of the successful combination of advanced lock-in thermography analysis and high resolution 3D X-ray for totally non-destructive defect location within a packaged device. This initial accurate thermal localization in x, y and z enables the high resolution 3D X-ray system to focus analysis to a few microns so that the defect can be seen quickly (< 1 hr), enabling detection and analysis of previously undetected defects with highest throughput.


Author(s):  
Gregory M. Johnson ◽  
Christopher D’Aleo ◽  
Ziyan Xu ◽  
Unoh Kwon ◽  
Harvey Berman ◽  
...  

Abstract Semiconductor Test Site structures were analyzed using an EBIRCH (Electron Beam Induced Resistance CHange) system. Localization of a RX (active area) to PC (gate) short was achieved with resolution that surpassed that of OBIRCH (Optical Beam Induced Resistance CHange). A voltage breakdown test structure at Metal 1 was stressed in the system, giving isolation to the specific contact. A five-fin diode macro was examined, and it is believed that the electrically active diffusions were imaged as individual fins from Metal 1. A series of ring oscillator devices were examined in steady state condition, and careful consideration of the image supports a hypothesis that Seebeck effect, from heating material interfaces in an EBIRCH system, is the reason for the “dipoles” reported in earlier literature.


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