Energy-Efficient Hybrid Unicore Architecture In Future Embedded Chip-Multiprocessor

2021 ◽  
Author(s):  
Akram Hadeed
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Energy Efficient ◽  
Access Time ◽  
Hybrid Architecture ◽  
Operational Parameters ◽  
Power Budget ◽  
Voltage Frequency ◽  
Run Time ◽  
On Chip

Recently, technology scaling has enabled the placement of an increasing number of cores, in the form of chip-multiprocessors (CMPs) on a chip and continually shrinking transistor sizes to improve performance. In this context, power consumption has become the main constraint in designing CMPs. As a result, uncore components power consumption taking increasing portion from the on-chip power budget; therefore, designing power management techniques, particularly memory and network-on-chip (NoC) systems, has become an important issue to solve. Consequently, a considerable attention has been directed toward power management based on CMPs components, particularly shared caches and uncore interconnected structures, to overcome the challenges of limited chip power budget.<div>This work targets to design an energy-efficient uncore architecture by using heterogeneity in components (cache cells) and operational parameters (Voltage/Frequency). In order to ensure the minimum impact on the system performance, a run-time approach is investigated to assess the proposed method. An architecture is proposed where the cache layer contains the heterogenous cache banks in all placed in one frequency voltage domain. Average memory access time (AMAT) was selected as a network monitor to monitor the performance on the run-time. The appropriate size and type of the last level cache (LLC) and Voltage/Frequency for the uncore domain is adjusted according to the calculated AMAT which indicates the system demand from the uncore.<br></div><div>The proposed hybrid architecture was implemented, investigated and compared with the a baseline model where only SRAM banks were used in the last level cache. Experimental results on the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suit,show that the proposed architecture yields up to a 40% reduction in overall chip energy-delay product with a marginal performance degradation in average of -1.2% below the baseline one. The best energy saving was 55% and the worse degradation was only 15%.<br></div>

scholarly journals Energy-Efficient Hybrid Unicore Architecture In Future Embedded Chip-Multiprocessor

2021 ◽  
Author(s):  
Akram Hadeed
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Energy Efficient ◽  
Access Time ◽  
Hybrid Architecture ◽  
Operational Parameters ◽  
Power Budget ◽  
Voltage Frequency ◽  
Run Time ◽  
On Chip

Recently, technology scaling has enabled the placement of an increasing number of cores, in the form of chip-multiprocessors (CMPs) on a chip and continually shrinking transistor sizes to improve performance. In this context, power consumption has become the main constraint in designing CMPs. As a result, uncore components power consumption taking increasing portion from the on-chip power budget; therefore, designing power management techniques, particularly memory and network-on-chip (NoC) systems, has become an important issue to solve. Consequently, a considerable attention has been directed toward power management based on CMPs components, particularly shared caches and uncore interconnected structures, to overcome the challenges of limited chip power budget.<div>This work targets to design an energy-efficient uncore architecture by using heterogeneity in components (cache cells) and operational parameters (Voltage/Frequency). In order to ensure the minimum impact on the system performance, a run-time approach is investigated to assess the proposed method. An architecture is proposed where the cache layer contains the heterogenous cache banks in all placed in one frequency voltage domain. Average memory access time (AMAT) was selected as a network monitor to monitor the performance on the run-time. The appropriate size and type of the last level cache (LLC) and Voltage/Frequency for the uncore domain is adjusted according to the calculated AMAT which indicates the system demand from the uncore.<br></div><div>The proposed hybrid architecture was implemented, investigated and compared with the a baseline model where only SRAM banks were used in the last level cache. Experimental results on the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suit,show that the proposed architecture yields up to a 40% reduction in overall chip energy-delay product with a marginal performance degradation in average of -1.2% below the baseline one. The best energy saving was 55% and the worse degradation was only 15%.<br></div>

scholarly journals Nodal Level Adaptive Security for IOT-Enabled Sensors through Dynamic Reconfigurable Encryption

2019 ◽  
Vol 8 (6) ◽  
pp. 2574-2577
Keyword(s):  
Energy Efficient ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Security Level ◽  
Adaptive Security ◽  
Power Budget ◽  
Dynamically Reconfigurable ◽  
Dynamic Encryption ◽  
On Chip ◽  
Nodal Level

IOT-enabled sensors have been deployed in the wide area to perform various applications. Information security is an important aspect in wireless sensor networks. Since the attackers can be able to hack the information even at the node level, improved security mechanism have to be implemented. In this paper, nodal level security is done through dynamic encryption technique. The advantage of dynamic encryption is achieved by adaptive security. The proposed method involves a system-on-chip (SoC) design to provide a dynamically reconfigurable encryption methodology which leads to improved security level and also the energy efficiency. Dynamic encryption creates the confusion among the hackers about the tracking of security keys. The results shows that by dynamically selecting the encryption module through soft-core processor based on the available power budget, an energy efficient security solution is obtained for sensor nodes with reduced resources utilization.

Efficient Scratchpad Memory Management for Mobile Multimedia Application

2013 ◽  
Vol 748 ◽  
pp. 932-935
Author(s):  
Ze Yu Zuo ◽  
Wei Hu ◽  
Rui Xin Hu ◽  
Heng Xiong ◽  
Wen Bin Du ◽  
...  
Keyword(s):  
Power Consumption ◽  
Mobile Devices ◽  
Memory Management ◽  
Multimedia Applications ◽  
Access Time ◽  
Management Approach ◽  
Mobile Multimedia ◽  
Scratchpad Memory ◽  
Mobile Multimedia Application ◽  
On Chip

Mobile devices have been popular in recent years and the proliferation of mobile devices inspires the interest in mobile multimedia applications. However, memory is always the bottleneck in the traditional memory hierarchy. Scratchpad memory (SPM) is a promising on-chip SRAM to solve such problem. It has faster access time and less power-consumption compared to cache and off-chip memory. In this paper, we propose the efficient scratchpad memory management approach for mobile multimedia applications. SPM is partitioned for the assignment of the slices of the applications based on the profiling and the recorded history. Through the use of SPM, the memory footprint of mobile multimedia applications will be reduced for better performance and less power-consumption. The experimental results show that our approach is able to significantly reduce the power consumption and improve the performance of mobile multimedia applications.

scholarly journals Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1821
Author(s):  
Sandy A. Wasif ◽  
Salma Hesham ◽  
Diana Goehringer ◽  
Klaus Hofmann ◽  
Mohamed A. Abd El Ghany
Keyword(s):  
Power Consumption ◽  
Double Layer ◽  
Energy Efficient ◽  
High Performance ◽  
Data Transfer ◽  
Low Frequency ◽  
Asynchronous Circuit ◽  
Two Phase ◽  
Phase Layer ◽  
On Chip

A network-on-chip (NoC) offers high performance, flexibility and scalability in communication infrastructure within multi-core platforms. However, NoCs contribute significantly to the overall system’s power consumption. The double-layer energy efficient synchronous-asynchronous circuit-switched NoC (CS-NoC) is proposed to enhance the power utilization. To reduce the dynamic power consumption, single-rail asynchronous protocols are utilized. The two-phase and four-phase encoding algorithms are analyzed to determine the most efficient technique. For the data layer, the two asynchronous protocols reduced the power consumption by 80%, with an increase in latency when compared with the fully synchronous protocol. However, the two-phase single-rail protocol had better performance compared with the four-phase protocol by 38%, with the same power consumption and a slight increase in area of 5%. Based on this conducted analysis, the asynchronous two-phase layer had significant power reduction yet operated at a moderate frequency. Therefore, the proposed NoC is divided into two data transfer layers with a single control layer. The data transfer layers are designed using synchronous and asynchronous protocols. The synchronous layer is designated to high-frequency loads, and the asynchronous layer is confined to low-frequency loads. The switching between the layers creates a trade-off between the maximum allowed frequency and the power consumption. The proposed NoC reduces the overall power consumption by 23% when compared with recent previous work. The NoC maintains the same system performance with an 8% area increase over the fully synchronous double-layer in the literature.

scholarly journals A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

2021 ◽  
Vol 2021 ◽  
pp. 1-20
Author(s):  
Dimple Sharma ◽  
Lev Kirischian
Keyword(s):  
Decision Making ◽  
Power Consumption ◽  
Thermal Cycling ◽  
Mobile Systems ◽  
Structural Adaptation ◽  
Estimation Model ◽  
Power Budget ◽  
Potential System ◽  
Die Temperature ◽  
Run Time

Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads. For such field-deployed systems, activation times, execution periods of tasks, and variations in environmental conditions are usually difficult to predict. These dynamic variations result in a new challenge of dynamic thermal cycling stress on the SoPC die, which can result in transient and even permanent hardware faults in the computing system. This paper proposes the approach of run-time structural adaptation (RTSA) to mitigate dynamic thermal cycling stress on the SoPC dies. RTSA assumes the tasks to have multiple implementation variants, called Application Specific Processing (ASP) circuit variants, which vary in hardware resources, operating frequency, and power consumption. Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of operation. This means the essence of RTSA is a decision-making mechanism which can select at run-time, a suitable system configuration (set of ASP circuit variants of active tasks), whenever needed, to meet the die temperature constraints. To do so, run-time die temperature prediction for potential system configurations using an estimation model is required. This paper presents a generic method to derive an analytical model for any SoPC that can estimate the die temperature in real time and thus support the decision-making mechanism. To develop this method, the thermal behavior of SoPC die under different task scenarios is studied and relation of die temperature to frequency, resource utilization, and power consumption is analyzed. An RTSA-enabled experimental platform is set up on Xilinx Zynq XC7Z020 SoPC for this purpose. Experimental results also demonstrate that the proposed method can be used to derive a model in run-time, thus enabling systems to self-derive and dynamically update the model in run-time.

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