scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

scholarly journals A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 375
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Successive Approximation ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Adaptive Power

A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

scholarly journals Comparison of 4-Bit SAR ADC Using Different Logic Styles in 90nm Technology

2021 ◽  
pp. 100-108
Author(s):  
Mrs. Lakshmidevi TR ◽  
Mr. K N Jeevan Reddy ◽  
Mr. Ashrith Rao ◽  
Mr. Dhanush Kashyap S ◽  
Ms. Chandini K
Keyword(s):  
Successive Approximation ◽  
Logic Gates ◽  
Design Tool ◽  
Sar Adc ◽  
Analog To Digital Converters ◽  
Battery Life ◽  
Double Pass ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Tool Building

In recent years, we have come across a growing need for the design of low power, long battery life Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC). ADCs are the major component of all the systems which need to process an analogue signal obtained from measuring real world parameters and hence they need to be efficient enough depending on the application and power constraint of the device. Speed is also an important parameter as it is used in many real time applications. The basic components of the SAR ADC can be implemented using circuits of various logics available for the logic gates, adders, comparators utilised in it. This paper presents the working of 4-bit successive approximation register analog-to-digital converters (SAR ADC) in three different logics namely, Complementary Metal Oxide Semiconductors (CMOS), Transmission Gates (TG), and Double Pass Transistors (DPL) logics, which were used in the basic components of each major block of the ADC. The aim of this paper here is to compare the various parameters such as area, power consumption and delay between the three different technologies chosen above. The SAR ADCs were implemented for this purpose in 90nm Technology using the Cadence Virtuoso Design Tool building schematics and layouts for the same and calculating the various parameters required for the above-mentioned comparison.

A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications

2018 ◽  
Vol 27 (14) ◽  
pp. 1850230 ◽  
Author(s):  
Samaneh Babayan-Mashhadi ◽  
Mona Jahangiri-Khah
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Power Saving ◽  
Cmos Technology ◽  
Sar Adc ◽  
Signal Acquisition ◽  
Quantization Scheme ◽  
Power Efficient ◽  
Sensing Applications

As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18[Formula: see text][Formula: see text]m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25[Formula: see text]kS/s, the proposed 8-bit ADC consumes 260[Formula: see text]nW of power from 1.8[Formula: see text]V supply voltage while achieving 7.1 effective number of bits.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

scholarly journals Design of 12-Bit SAR ADC using Split Capacitor Based DAC Architecture at 45nm CMOS Technology

2019 ◽  
Vol 8 (12) ◽  
pp. 2530-2535
Keyword(s):  
Successive Approximation ◽  
Medical Application ◽  
Cmos Technology ◽  
Sar Adc ◽  
Performance Parameters ◽  
Digital Converter ◽  
Analog To Digital ◽  
Common Mode Voltage ◽  
Split Capacitor ◽  
Increasing Demand

Nowadays, there is an increasing demand for Successive Approximation Register (SAR) based Analog to Digital Converter (ADC) in long battery applications like medical application, Sensors and many more. In this paper DAC circuit is designed using multiple capacitor and Multiple MUX for switching. A split based capacitor is used for boosting the speed of the architecture. In split based DAC no common mode voltage required and dynamic offset can be removed as well. In this work, 12-Bit DAC and encoder is designed using 2 Transistor MUX and 18 Transistor Full adders (12B-2TM-18TFA). 2T and 18T is used to design the MUX and FA. This entire architecture is implemented in Cadence Virtuoso 45nm CMOS technology. Simultaneously, 10B-12TM-36TFA architecture also implemented in this paper. The performance parameters like area, power, and delay, current is evaluated for both architectures. Result showed that 12B-2TM-18TFA architecture consumed less area, less power, less delay, and less current compared to 10B-12TM-36TFA.

A Successive Approximation Register Analog to Digital Converter for Low Power Applications

2020 ◽  
Vol 17 (1) ◽  
pp. 451-455
Author(s):  
Yahya Mohammed Ali Al-Naamani ◽  
K. Lokesh Krishna ◽  
A. M. Guna Sekhar
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Research Work ◽  
Implantable Devices ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Analog To Digital ◽  
Successive Approximation Register

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

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