scholarly journals High Level FPGA Implementation Of Adaptive Signal Segmentation And Autoregressive Modeling Techniques

2021 ◽  
Author(s):  
Beibei. Jiao
Keyword(s):  
Double Precision ◽  
Autoregressive Modeling ◽  
Biomedical Signals ◽  
Signal Segmentation ◽  
Modeling Techniques ◽  
Lattice Algorithm ◽  
High Level ◽  
Ar Modeling ◽  
Adaptive Signal ◽  
Point Arithmetic

This thesis contains new FPGA implementations of adaptive signal segmentation and autoregressive modeling techniques. Both designs use Simulink-to-FPGA methodology and have been successfully implemented onto Xilinx Virtex II Pro device. The implementation of adaptive signal segmentation is based on the conventional RLSL algorithm using double-precision floating point arithmetic for internal computation and is programmable for users providing data length and order selection functions. The implemented RLSL design provides very good performance of obtaining accurate conversion factor values with a mean correlation of 99.93% and accurate boundary positions for both synthesized and biomedical signals. The implementation of autoregressive (AR) modeling is based on the Burg-lattice algorithm using fixed point arithmetic. The implemented Burg design with order of 3 provides good performance of calculating AR coefficients of input biomedical signals.

scholarly journals High Level FPGA Implementation Of Adaptive Signal Segmentation And Autoregressive Modeling Techniques

2021 ◽  
Author(s):  
Beibei. Jiao
Keyword(s):  
Double Precision ◽  
Autoregressive Modeling ◽  
Biomedical Signals ◽  
Signal Segmentation ◽  
Modeling Techniques ◽  
Lattice Algorithm ◽  
High Level ◽  
Ar Modeling ◽  
Adaptive Signal ◽  
Point Arithmetic

This thesis contains new FPGA implementations of adaptive signal segmentation and autoregressive modeling techniques. Both designs use Simulink-to-FPGA methodology and have been successfully implemented onto Xilinx Virtex II Pro device. The implementation of adaptive signal segmentation is based on the conventional RLSL algorithm using double-precision floating point arithmetic for internal computation and is programmable for users providing data length and order selection functions. The implemented RLSL design provides very good performance of obtaining accurate conversion factor values with a mean correlation of 99.93% and accurate boundary positions for both synthesized and biomedical signals. The implementation of autoregressive (AR) modeling is based on the Burg-lattice algorithm using fixed point arithmetic. The implemented Burg design with order of 3 provides good performance of calculating AR coefficients of input biomedical signals.

scholarly journals The Effectiveness Of Behavioral Concept With Modeling Techniques Through Lesson Study To Improve Self Nurturance Of Class X BDPM A Students State SMK Negeri 1 Singaraja

2019 ◽  
Vol 3 (1) ◽  
pp. 18
Author(s):  
Ngurah Adi Mahendra ◽  
I Ketut Dharsana ◽  
Ni Ketut Suarni
Keyword(s):  
Lesson Study ◽  
Hypothesis Test ◽  
T Test ◽  
The Self ◽  
Control Group ◽  
Validity And Reliability ◽  
Control Group Design ◽  
Behavioral Counseling ◽  
Modeling Techniques ◽  
High Level

The purpose of this study was to determine the effectiveness of Behavioral Counseling with a modeling technique through lesson study to improve Self Nurturance in class X BDPM A SMK Negeri 1 Singaraja. This research includes "quasi experiment". The experimental design used was Pretest Postest Control Group Design. The population of this research is 71 grade X students of SMK Negeri 1 Singaraja. Through random sampling techniques, 34 students were placed in the experimental group and 37 students were placed in the control group. The method of data collection in this study used the method of observation, interviews, diaries and the Self Nurturance questionnaire. The self nurturance questionnaire has been tested for its validity and reliability. Analysis of questionnaire data using the Cronbach Alpha method. The study used the Independent Samples t-test with the help of JASP Version 0.7.5.5 showing the value of the hypothesis test results using Independent Samples t-test, getting t = 9,347 with p <0.05. Effect Size (ES) testing shows a high level of effectiveness (ES = 2.221). These results prove that behavioral counseling with effective modeling techniques to improve Self Nurturance class X students at SMK Negeri 1 Singaraja.

Operational Single-Precision Earth-System Modelling at ECMWF

2021 ◽  
Author(s):  
Sam Hatfield ◽  
Kristian Mogensen ◽  
Peter Dueben ◽  
Nils Wedi ◽  
Michail Diamantakis
Keyword(s):  
Atmospheric Model ◽  
Floating Point ◽  
System Modelling ◽  
Double Precision ◽  
Earth System ◽  
Single Precision ◽  
System Models ◽  
Floating Point Arithmetic ◽  
Point Arithmetic ◽  
Earth System Models

&lt;p&gt;Earth-System models traditionally use double-precision, 64 bit floating-point numbers to perform arithmetic. According to orthodoxy, we must use such a relatively high level of precision in order to minimise the potential impact of rounding errors on the physical fidelity of the model. However, given the inherently imperfect formulation of our models, and the computational benefits of lower precision arithmetic, we must question this orthodoxy. At ECMWF, a single-precision, 32 bit variant of the atmospheric model IFS has been undergoing rigorous testing in preparation for operations for around 5 years. The single-precision simulations have been found to have effectively the same forecast skill as the double-precision simulations while finishing in 40% less time, thanks to the memory and cache benefits of single-precision numbers. Following these positive results, other modelling groups are now also considering single-precision as a way to accelerate their simulations.&lt;/p&gt;&lt;p&gt;In this presentation I will present the rationale behind the move to lower-precision floating-point arithmetic and up-to-date results from the single-precision atmospheric model at ECMWF, which will be operational imminently. I will then provide an update on the development of the single-precision ocean component at ECMWF, based on the NEMO ocean model, including a verification of quarter-degree simulations. I will also present new results from running ECMWF's coupled atmosphere-ocean-sea-ice-wave forecasting system entirely with single-precision. Finally I will discuss the feasibility of even lower levels of precision, like half-precision, which are now becoming available through GPU- and ARM-based systems such as Summit and Fugaku, respectively. The use of reduced-precision floating-point arithmetic will be an essential consideration for developing high-resolution, storm-resolving Earth-System models.&lt;/p&gt;

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

2016 ◽  
Vol 5 (2) ◽  
pp. 118
Author(s):  
J. Vijay Kumar ◽  
B. Naga Raju ◽  
M. Vasu Babu ◽  
T. Ramanjappa
Keyword(s):  
Low Power ◽  
Arithmetic Operation ◽  
Floating Point ◽  
Double Precision ◽  
Verilog Hdl ◽  
Logical Function ◽  
Floating Point Arithmetic ◽  
Risc Processor ◽  
Operation Results ◽  
Point Arithmetic

This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device.  The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

scholarly journals High-Level Synthesis under Fixed-Point Accuracy Constraint

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Daniel Menard ◽  
Nicolas Herve ◽  
Olivier Sentieys ◽  
Hai-Nam Nguyen
Keyword(s):  
Signal Processing ◽  
Fixed Point ◽  
Word Length ◽  
High Level Synthesis ◽  
Floating Point ◽  
Fixed Point Arithmetic ◽  
Resource Binding ◽  
High Level ◽  
Point Arithmetic ◽  
Length Optimization

Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%.

Implementation of Embedded Floating Point Arithmetic Units on FPGA

2014 ◽  
Vol 550 ◽  
pp. 126-136
Author(s):  
N. Ramya Rani
Keyword(s):  
High Speed ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Embedded Computing ◽  
Floating Point Arithmetic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Arithmetic Units ◽  
Point Arithmetic

:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper, methodologies are presented for the implementation of embedded floating point units on FPGA. The work is focused with the aim of achieving high speed of computations and to reduce the power for evaluating expressions. An application that demands high performance floating point computation can achieve better speed and density by incorporating embedded floating point units. Additionally this paper describes a comparative study of the design of single precision and double precision pipelined floating point arithmetic units for evaluating expressions. The modules are designed using VHDL simulation in Xilinx software and implemented on VIRTEX and SPARTAN FPGAs.

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