Reduction of Random Dopant Fluctuation-induced Variation in Junctionless FinFETs via Negative Capacitance Effect

In this paper, we investigate the impact of random dopant fluctuation (RDF) on the statistical variations in negative capacitance MOSFETs (NCFETs) through a device simulation coupled with the Landau–Khalatnikov (LK) equation. Compact models for feedback mechanisms that are based on the internal gate voltage amplification in NCFETs are proposed. The results show that internal voltage amplification plays a decisive role in performance improvement of device variability. Further, our simulation study demonstrates that owing to the feedback mechanism, the dispersions of the performance parameters in NCFETs exhibit different statistical distribution characteristics compared to their MOSFET counterparts. Our study may provide further insight regarding device and/or circuit designs utilizing NCFETs.

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Performance improvement of timing and power variations due to random dopant fluctuation in negative-capacitance CMOS inverters

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2020.0101 ◽

2020 ◽

Vol 14 (6) ◽

pp. 908-914

Author(s):

Kai Zhang ◽

Weifeng Lü ◽

Peng Si ◽

Zhifeng Zhao ◽

Tianyu Yu

Keyword(s):

Performance Improvement ◽

Negative Capacitance ◽

Random Dopant Fluctuation ◽

Random Dopant

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Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET

Electronics ◽

10.3390/electronics10161899 ◽

2021 ◽

Vol 10 (16) ◽

pp. 1899

Author(s):

Yejoo Choi ◽

Jinwoong Lee ◽

Jaehyuk Lim ◽

Seungjun Moon ◽

Changhwan Shin

Keyword(s):

Work Function ◽

Device Performance ◽

Negative Capacitance ◽

Line Edge Roughness ◽

Random Dopant Fluctuation ◽

Edge Roughness ◽

The Impact ◽

Random Dopant

In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS], σ[Ion/Ioff], σ[Vt]/µ[Vt], σ[SS]/µ[SS], and σ[Ion/Ioff]/µ[Ion/Ioff], and enhanced device performance, which implies that the NC effect can successfully control the variation-induced degradation.

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On the Physical Mechanism of Negative Capacitance Effect in Ferroelectric FET

2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) ◽

10.23919/sispad49475.2020.9241628 ◽

2020 ◽

Author(s):

Masaharu Kobayashi

Keyword(s):

Physical Mechanism ◽

Negative Capacitance ◽

Capacitance Effect

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Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096513666201208102615 ◽

2020 ◽

Vol 13 ◽

Author(s):

Kai Zhang ◽

Weifeng Lü ◽

Peng Si ◽

Zhifeng Zhao ◽

Tianyu Yu

Keyword(s):

Monte Carlo ◽

Integrated Circuits ◽

Metal Oxide ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Gate Bias ◽

Cmos Inverter ◽

Back Gate ◽

Random Dopant Fluctuation ◽

Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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