DIGITAL SIMULATOR OF GPS C/A SIGNALS

2021 ◽  
pp. 64-78
Author(s):  
A. V. Ryapolov ◽  
V. E. Mitrokhin ◽  
N. V. Fambulov ◽  
D. A. Gredyaev
Keyword(s):  
Hardware Implementation ◽  
Digital Signal ◽  
Signal Simulator ◽  
Navigation Signals

A structure of a digital signal simulator which allows generating testing GPS C/A signals or creating signal-like interference is observed. Proposed scheme of the simulator includes generators of navigation signals, a generator of noiselike signal, a signal summation block and a block of signal bit capacity transformation. A vari-ant of simulator hardware implementation in FPGA is showed. Examples of gener-ated signals are presented.

Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator

2012 ◽  
Vol 1 (1) ◽  
pp. 37 ◽  
Author(s):  
Tole Sutikno ◽  
Aiman Zakwan Jidin ◽  
Auzani Jidin ◽  
Nik Rumzi Nik Idris
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Square Root ◽  
Main Principle ◽  
Hardware Resource ◽  
Root Operation ◽  
Hardware Designs

Square root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior.

scholarly journals SOME ASPECTS OF INCREASING THE PROCESSING POWER OF THE DIGITAL SIGNAL PROCESSORS

2014 ◽  
pp. 87-95
Author(s):  
Alexander Palagin ◽  
Miroslav Semotiuk ◽  
Yaroslav Vizor ◽  
Eugeniy Chichirin
Keyword(s):  
Hardware Implementation ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Equation Solving ◽  
Processing Power ◽  
Non Linear Equation ◽  
Hardware Overhead ◽  
Arithmetic Units ◽  
Signal Processors ◽  
Minimal Hardware

An analysis of the non-linear equation solving methods used by the arithmetic units of the computing devices was conducted in order to facilitate creation of the arithmetic units which would be optimal in terms of processing power and hardware overhead. A method and algorithm of a hardware implementation of computing the particular and the reciprocal in the digital signal processors at higher speed and minimal hardware overhead.

scholarly journals High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1451
Author(s):  
Asep Muhamad Awaludin ◽  
Harashta Tatimma Larasati ◽  
Howon Kim
Keyword(s):  
Elliptic Curve ◽  
Digital Signal Processor ◽  
Execution Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Low Complexity ◽  
Montgomery Ladder ◽  
Modular Multiplier ◽  
Pipelined Multiplier

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

scholarly journals Performing Text – To – Speech based Hidden Markov Model on Digital Signal Processing platform

2014 ◽  
Vol 17 (1) ◽  
pp. 32-38
Author(s):  
Nhat Truong Minh Vu ◽  
Binh Hieu Nguyen ◽  
Nhat Minh Pham ◽  
Thuan Huu Huynh ◽  
Tu Trong Bui ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Markov Model ◽  
Hidden Markov Model ◽  
Hardware Implementation ◽  
Hidden Markov ◽  
Digital Signal ◽  
Text To Speech ◽  
Processing Platform

Text To Speech (TTS) using Hidden Markov Model (HMM) has become popular in recent years. However, because most of such systems were implemented on personal computers (PCs), it is difficult to offer these systems to real applications. In this paper, we present a hardware implementation of TTS based on DSP architecture, which is applicable for real applications. By optimizing hardware architecture, the quality of the DSP-based synthesized speech is nearly identical to that synthesized on PCs.

scholarly journals SIMULATION OF AN ADARTIVE FILTER BASED ON THE RECURSIVE LEAST SQUARES METHOD

2021 ◽  
Vol 2 (39) ◽  
pp. 82-91
Author(s):  
О. Sotnik ◽  
S. Marchenko ◽  
О. Hulesha ◽  
О. Syanov
Keyword(s):  
Simulation Model ◽  
Least Squares ◽  
Design Process ◽  
High Speed ◽  
Hardware Implementation ◽  
Least Squares Method ◽  
Digital Signal ◽  
Recursive Least Squares ◽  
Optimal Order ◽  
Recursive Least Squares Method

Modern electronics systems are high-speed, compact and require the use of energy-efficient digital electronics devices (DED’s) such as microcontrollers, programmable logic integrated circuits (FPGA’s), digital signal processors. Application of  the  DED’s  is a hardware implementation of high - performance digital signal processing (DSP) algorithms based on the target architecture of the electronic device. In order to accellarate of the design process in the  direct hardware implementation of  DSP algorithms, simulation models are created to enable optimizing the design process at the stage of a creation of the  programming part for FPGA. The paper presents the results of a study of the adaptive filter (AF) model based on the recursive least squares method (RLS). According to the analysis of time and frequency parameters of the AF model has been conducted  during  simulation it was found that the qualitative filtering process starting from the 24th order and further increasing the AF order does not significantly improve signal filtering, but only increases the required hardware resources. In process of the verification of the proposed simulation model, the AF-based noise reduction system has been modeled and the  THD  level of 7.103 % was obtained for the built-in AF unit, which is more than one and a half times higher than the proposed AF unit 4.323 %, which confirmed the efficiency of the developed AF unit. Thus, during the study, the optimal order of AF has been determined, which will allow more efficient use of FPGA resources during the hardware implementation of AF. In accordance with the results of the study, the correctness and efficiency of the created hardware-oriented simulation model has been proved, as well as the hardware-oriented structure of the adaptive RLS filter for future implementation on FPGA nas been shown.

Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device

2017 ◽  
Vol 6 (01) ◽  
pp. 14-19
Author(s):  
Prof. Parvaneh Basaligheh
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Digital Systems ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
High Speeds ◽  
Vedic Multiplier ◽  
High Level

Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.

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