Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device

2017 ◽  
Vol 6 (01) ◽  
pp. 14-19
Author(s):  
Prof. Parvaneh Basaligheh
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Digital Systems ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
High Speeds ◽  
Vedic Multiplier ◽  
High Level

Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.

Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

2013 ◽  
Vol 2 (1) ◽  
pp. 15
Author(s):  
Sachin B. Jadhav ◽  
Jayamala K. Patil ◽  
Ramesh T. Patil
Keyword(s):  
Binary Tree ◽  
High Speed ◽  
Hardware Implementation ◽  
Critical Path ◽  
Partial Product ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
Multiplication Process ◽  
Major Bottleneck ◽  
Speed Up

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

scholarly journals Comparative Analysis of Multiplications Technique Conventional, Booth, Array Multiplier and Vedic Arithmetic Using VHDL

2021 ◽  
Author(s):  
Akash Kumar ◽  
Tarun Chaudhary ◽  
Vijay Kumar Ram
Keyword(s):  
Signal Processing ◽  
Comparative Analysis ◽  
Digital Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Electronic Devices ◽  
Digital Signal ◽  
Booth Multiplier ◽  
Multiplication Operation ◽  
Array Multiplier

The multiplication operation is one of the often used operation in many computer and electronic devices. Low power utilization is one of the most essential attributes for meeting several challenges in many applications. In this paper different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processing, so designing a high speed multiplier is the need the hour. Structures of 4X4 bits Urdhva Tiryagbhya, Nikhilam Sutra have been executed on Spartan 3 XC3S50-5-PQ-208.The determined calculation delay for 4X4 Urdhva Tiryagbhyam was 14.14 ns and force is 20.60 mw. For Nikhilam Sutra the determined computational postponement is 16.16 ns and all out force utilization is 24.60 mw.

scholarly journals Design and Analysis of Multiplier Using High Speed Adders

2021 ◽  
pp. 68-75
Author(s):  
Swetha R ◽  
Priyanka M ◽  
Suvetha S ◽  
Kavitha S
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Digital Filters ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Systems ◽  
Operating Speed ◽  
Look Ahead ◽  
Dsp Applications ◽  
Multiplier Circuit

In all digital signal processing (DSP) applications like FFT, digital filters the main problem faced by processor is its propagation delay. Every high speed signal processing is depends on multiplier circuits. Multiplier performance is directly influenced by the adder design. In this paper, we design low power and high speed carry look ahead (CLA) adder for multiplier circuit by using multi value logic (MVL) based on quaternary signed digits (QSD). The ability of multi value logic (MVL) circuits to achieve more information density and high operating speed when compared to that of existing binary circuits is highly impressive. MVL circuits have attracted important attention for the design of digital systems. Based on quaternary signed digits, the carry look ahead adder is designed, implemented in multiplier circuit and simulated by using cadence virtuoso design suite by 180nF technology.

scholarly journals Reversible Vedic Multiplier

2019 ◽  
Vol 8 (6S2) ◽  
pp. 852-857
Keyword(s):  
Embedded System ◽  
High Speed ◽  
Digital Signal ◽  
Design Parameters ◽  
Design Constraint ◽  
Performance Constraints ◽  
Multiplication Operation ◽  
Vedic Multiplier ◽  
Essential Components ◽  
Almost All

In the new era of technology speed effective advanced multiplier has greatest demand, where they acts as an essential part in almost all high speed processing units which are used currently. As the multiplier is one of the essential components in several computing machines, for instant microprocessors, DSPs (Digital Signal Processors) and quantum computational and combinational systems. The performances of different processors is measured based on number of multiplication completed per second. So efficient multiplier designs are to be found to meet these performance constraints and one such approach which provides solution to above problem is Vedic multiplier. It is simple in structure and increase the efficiency by reducing the unnecessary steps in multiplication. Furthermore, implementing the designed multiplier using reversible gates can decreases the dissipation of power also, which is another essential design constraint that to be met in an embedded system. In the present work, a 4X4 reversible Vedic multiplier is designed; moreover it can offers more efficiency in terms of reversible design parameters such as TRLIC (Total Reversible Logic Implementation Cost) and delay. Code for 4X4 Vedic multiplication operation is written using Verilog HDL programming language and simulation is done using Xilinx 14.7 ISE is targeted to selected FPGA device family as Vertex 6

Design and Implementation of Recursive Least Square Adaptive Filter Using Block DCD approach

2015 ◽  
Vol 4 (3) ◽  
pp. 209
Author(s):  
Sachin S. Khanande ◽  
S.J. Honade
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Adaptive Filter ◽  
High Speed ◽  
Large Scale ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Least Square ◽  
Recursive Least Square ◽  
Design And Implementation

<p>Due to the explosive growth of multimedia application and tremendous demands in Very Large Scale Integrated (VLSI), there is a need of high speed and low power digital filters for digital signal processing applications. In Digital Signal Processing (DSP) systems, Finite Impulse Response (FIR) filters are one of the most common components which is used, by convolving the input data samples with the desired unit sample response of the filter. The proposed work deals with the design and implementation of RLS adaptive filter using block DCD approach. The evaluation of speed, area and power for proposed work will be done. Also, the comparison of the proposed design with the existing will be carried out for various input combinations.</p>

scholarly journals An efficient hardware logarithm generator with modified quasi-symmetrical approach for digital signal processing

2020 ◽  
Vol 10 (5) ◽  
pp. 4671
Author(s):  
Minh-Hong Nguyen
Keyword(s):  
Signal Processing ◽  
Error Analysis ◽  
Digital Signal Processing ◽  
Real Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Approximation Error ◽  
Digital Signal ◽  
Traditional Methods ◽  
Low Area

This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.

scholarly journals Three-Axis Inductive Displacement Sensor Using Phase-Sensitive Digital Signal Processing for Industrial Magnetic Bearing Applications

Actuators ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 115
Author(s):  
Teemu Sillanpää ◽  
Alexander Smirnov ◽  
Pekko Jaatinen ◽  
Jouni Vuojolainen ◽  
Niko Nevaranta ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Eddy Current ◽  
High Speed ◽  
Digital Signal ◽  
Magnetic Bearing ◽  
Air Gap ◽  
Sensor Design ◽  
Quadrature Demodulation ◽  
Displacement Sensors

Non-contact rotor position sensors are an essential part of control systems in magnetically suspended high-speed drives. In typical active magnetic bearing (AMB) levitated high-speed machine applications, the displacement of the rotor in the mechanical air gap is measured with commercially available eddy current-based displacement sensors. The aim of this paper is to propose a robust and compact three-dimensional position sensor that can measure the rotor displacement of an AMB system in both the radial and axial directions. The paper presents a sensor design utilizing only a single unified sensor stator and a single shared rotor mounted target piece surface to achieve the measurement of all three measurement axes. The sensor uses an inductive measuring principle to sense the air gap between the sensor stator and rotor piece, which makes it robust to surface variations of the sensing target. Combined with the sensor design, a state of the art fully digital signal processing chain utilizing synchronous in-phase and quadrature demodulation is presented. The feasibility of the proposed sensor design is verified in a closed-loop control application utilizing a 350-kW, 15,000-r/min high-speed industrial induction machine with magnetic bearing suspension. The inductive sensor provides an alternative solution to commercial eddy current displacement sensors. It meets the application requirements and has a robust construction utilizing conventional electrical steel lamination stacks and copper winding.

Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board

2015 ◽  
Vol 719-720 ◽  
pp. 534-537
Author(s):  
Wen Hua Ye ◽  
Huan Li
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
Processing System ◽  
Digital Signal ◽  
Signal Processing System ◽  
High Speed Adc ◽  
High Speed Data ◽  
Processor Speed ◽  
Signal Processor

With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.

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