scholarly journals HALF ADDER DESIGN USING VARIOUS TECHNOLOGIES AND COMPARISON OF

Author(s):  
Rituraj Yadav ◽  
Ashish Sura ◽  
Sunita Dahiya

: In this paper, investigate and analysis various techniques for implementing a half adder circuit with the fewest transistors possible. In digital electronics half adder combinational circuit used to add two numbers. It is an arithmetic circuit that performs the arithmetic operation of adding two single-bit words. The half adder technique, design of half adder using AVL technology, Design of a 3-T Half Adder, NMOS pass transistors logic design of half adder using 2:1 MUX, half adder circuit design with CMOS NAND gates, half adder circuit design with CMOS transmission logic gates in cadence virtuoso. In this section, compare half adder circuit design techniques and compare various parameters of half adder circuit design used various circuit design techniques. Conventional techniques required fewer number routing resources. A 3-T halfadder circuit performs with less delay, high speed, small layout area, less power consumption and batter efficiency and accuracy

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Ankur Saharia ◽  
Ashish Kumar Ghunawat ◽  
Manish Tiwari ◽  
Anton V. Bourdine ◽  
Vladimir A. Burdin ◽  
...  

AbstractAll-optical processor capable of processing optical bits has been a long-standing goal of photonics. In this paper, we report the results obtained by numerical simulations regarding the designing of an all-optical combinational circuit of an adder and subtractor circuits based on Si3N4 microring resonators. The designs of combinational circuit like adders and subtractor based on the use of all-optical basic logic gates are discussed while presenting the numerically simulated results. Extinction ratios of 5.2 dB, 3.5 dB and 2.7 dB are obtained for the half adder, full adder and half subtractor, respectively.


2014 ◽  
Vol 18 (6) ◽  
pp. 639-645 ◽  
Author(s):  
Simranjit Singh ◽  
Rajinder Singh Kaler ◽  
Rupinder Kaur

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Hamed Azhdari ◽  
Sahel Javahernia

Abstract Increasing the speed of operation in all optical signal processing is very important. For reaching this goal one needs high speed optical devices. Optical half adders are one of the important building blocks required in optical processing. In this paper an optical half adder was proposed by combining nonlinear photonic crystal ring resonators with optical waveguides. Finite difference time domain method wase used for simulating the final structure. The simulation results confirmed that the rise time for the proposed structure is about 1 ps.


Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1032
Author(s):  
Hyoungsik Nam ◽  
Young In Kim ◽  
Jina Bae ◽  
Junhee Lee

This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the improvement on the learning speed. The GateRL consists of an agent for the action and an environment for state, mask, and reward. State and reward are generated from a connection matrix that describes the current circuit configuration, and the mask is obtained from a masking matrix based on constraints and current connection matrix. The action is given rise to by the deep Q-network of 4 fully connected network layers in the agent. In particular, separate replay buffers are devised for success transitions and failure transitions to expedite the training process. The proposed network is trained with 2 inputs, 1 output, 2 NMOS transistors, and 2 PMOS transistors to design all the target logic gates, such as buffer, inverter, AND, OR, NAND, and NOR. Consequently, the GateRL outputs one-transistor buffer, two-transistor inverter, two-transistor AND, two-transistor OR, three-transistor NAND, and three-transistor NOR. The operations of these resultant logics are verified by the SPICE simulation.


2014 ◽  
Vol 2014 ◽  
pp. 1-20
Author(s):  
Bodhisatwa Sadhu ◽  
Martin Sturm ◽  
Brian M. Sadler ◽  
Ramesh Harjani

This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.


1995 ◽  
Vol 38 (3) ◽  
pp. 266-273 ◽  
Author(s):  
W.B. Hudson ◽  
J.S. Beasley ◽  
J.E. Steelman

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