scholarly journals A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1791
Author(s):  
Muhammad Ali Akbar ◽  
Bo Wang ◽  
Amine Bermak
Keyword(s):  
Fault Detection ◽  
High Speed ◽  
Parallel Architecture ◽  
Common Type ◽  
Area Overhead ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Area Product ◽  
Detection And Localization ◽  
Logic Unit

Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.

A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection

2019 ◽  
Vol 11 (1) ◽  
pp. 80-87 ◽  
Author(s):  
Jitendra Kumar Saini ◽  
Avireni Srinivasulu ◽  
Renu Kumawat
Keyword(s):  
Mass Production ◽  
High Speed ◽  
Field Effect Transistor ◽  
Full Adder ◽  
Enabling Technology ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Effect Transistor ◽  
Cad Tool ◽  
Power Delay Product

The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.

scholarly journals Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

2020 ◽  
Vol 12 (01) ◽  
pp. 8-12
Author(s):  
Md. Zakir Hussain ◽  
Kazi Nikhat Parvin
Keyword(s):  
Impulse Response ◽  
Software Defined Radio ◽  
High Speed ◽  
Finite Impulse Response ◽  
Finite Impulse Response Filters ◽  
Booth Multiplier ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Windowing Technique ◽  
Impulse Response Filters

This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

scholarly journals Design of high speed low power optimized square root BK adder

2018 ◽  
Vol 7 (2.12) ◽  
pp. 240
Author(s):  
Ranjith B Gowda ◽  
R M Banakar
Keyword(s):  
High Speed ◽  
Computation Time ◽  
Square Root ◽  
Digital World ◽  
Look Ahead ◽  
Course Work ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
Almost All ◽  
Design Cost

Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool. 

Image-Based Versus Signal-Based Sensors for Machine Fault Detection and Isolation

2014 ◽  
Author(s):  
Heshan Fernando ◽  
Vedang Chauhan ◽  
Brian Surgenor
Keyword(s):  
Fault Detection ◽  
High Speed ◽  
Fault Isolation ◽  
Video Data ◽  
Fault Detection And Isolation ◽  
Single Camera ◽  
Multiple Faults ◽  
Multiple Sensors ◽  
Machine Fault ◽  
And Performance

This paper presents the results of a comparative study that investigated the use of image-based and signal-based sensors for fault detection and fault isolation of visually-cued faults on an automated assembly machine. The machine assembles 8 mm circular parts, from a bulk-supply, onto continuously moving carriers at a rate of over 100 assemblies per minute. Common faults on the machine include part jams and ejected parts that occur at different locations on the machine. Two sensor systems are installed on the machine for detecting and isolating these faults: an image-based system consisting of a single camera and a signal-based sensor system consisting of multiple greyscale sensors and limit switches. The requirements and performance of both systems are compared for detecting six faults on the assembly machine. It is found that both methods are able to effectively detect the faults but they differ greatly in terms of cost, ease of implementation, detection time and fault isolation capability. The conventional signal-based sensors are low in cost, simple to implement and require little computing power, but the installation is intrusive to the machine and readings from multiple sensors are required for faster fault detection and isolation. The more sophisticated image-based system requires an expensive, high-resolution, high-speed camera and significantly more processing power to detect the same faults; however, the system is not intrusive to the machine, fault isolation becomes a simpler problem with video data, and the single camera is able to detect multiple faults in its field of view.

scholarly journals Thermal fault detection and localization framework for large format batteries

2021 ◽  
Vol 512 ◽  
pp. 230400
Author(s):  
Sara Sattarzadeh ◽  
Tanushree Roy ◽  
Satadru Dey
Keyword(s):  
Fault Detection ◽  
Large Format ◽  
Detection And Localization

scholarly journals PEM-PCA: A Parallel Expectation-Maximization PCA Face Recognition Architecture

2014 ◽  
Vol 2014 ◽  
pp. 1-16 ◽  
Author(s):  
Kanokmon Rujirakul ◽  
Chakchai So-In ◽  
Banchar Arnonkijpanich
Keyword(s):  
Feature Extraction ◽  
Face Recognition ◽  
Expectation Maximization ◽  
High Speed ◽  
Expectation Maximization Algorithm ◽  
Parallel Architecture ◽  
Principal Component ◽  
Eigenvalue Decomposition ◽  
Computational Time ◽  
Recognition Systems

Principal component analysis or PCA has been traditionally used as one of the feature extraction techniques in face recognition systems yielding high accuracy when requiring a small number of features. However, the covariance matrix and eigenvalue decomposition stages cause high computational complexity, especially for a large database. Thus, this research presents an alternative approach utilizing an Expectation-Maximization algorithm to reduce the determinant matrix manipulation resulting in the reduction of the stages’ complexity. To improve the computational time, a novel parallel architecture was employed to utilize the benefits of parallelization of matrix computation during feature extraction and classification stages including parallel preprocessing, and their combinations, so-called a Parallel Expectation-Maximization PCA architecture. Comparing to a traditional PCA and its derivatives, the results indicate lower complexity with an insignificant difference in recognition precision leading to high speed face recognition systems, that is, the speed-up over nine and three times over PCA and Parallel PCA.

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