scholarly journals A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1937
Author(s):  
Ying Zhang ◽  
Yubin Zhu ◽  
Kaining Han ◽  
Junchao Wang ◽  
Jianhao Hu
Keyword(s):  
Hardware Implementation ◽  
Finite Impulse Response ◽  
Signal To Noise Ratio ◽  
Digital Signal ◽  
Low Complexity ◽  
Fir Filter ◽  
Stream Length ◽  
Stochastic Computing ◽  
Dsp Systems ◽  
Bit Stream

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

Novel Methods to Design Low-Complexity Digital Finite Impulse Response (FIR) Filters

2018 ◽  
pp. 6234-6244
Author(s):  
David Ernesto Troncoso Romero ◽  
Gordana Jovanovic Dolecek
Keyword(s):  
Impulse Response ◽  
Digital Filters ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Low Complexity ◽  
Fir Filters ◽  
Linear Phase ◽  
Guaranteed Stability ◽  
Important Challenge ◽  
Dsp Systems

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Novel Methods to Design Low-Complexity Digital Finite Impulse Response (FIR) Filters

2019 ◽  
pp. 1053-1066
Author(s):  
David Ernesto Troncoso Romero ◽  
Gordana Jovanovic Dolecek
Keyword(s):  
Impulse Response ◽  
Digital Filters ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Low Complexity ◽  
Fir Filters ◽  
Linear Phase ◽  
Guaranteed Stability ◽  
Important Challenge ◽  
Dsp Systems

Digital filters play a central role in modern digital signal processing (DSP) systems. Finite impulse response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

scholarly journals EFFICIENT FINITE IMPULSE RESPONSE FILTER ARCHITECTURE USING MULTIPLE CONSTANT MULTIPLICATION AND COMMON SUB-EXPRESSION ELIMINATION TECHNIQUES

2017 ◽  
Vol 10 (13) ◽  
pp. 344
Author(s):  
Bhargav Shukla ◽  
Augusta Sophy Beulet
Keyword(s):  
Impulse Response ◽  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Computationally Efficient ◽  
Constant Multiplication ◽  
Dsp Systems ◽  
Fir Filter Design

This paper introduces the computationally efficient, low power, high-speed partial reconfigurable finite impulse response (FIR) filter design usingmultiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by MCM operation. Forthe better performance of DSP systems, MCM operation is not sufficient. To get better results, some other operations are used with MCM. That’s why,this paper introduces a common sub-expression elimination operation of FIR filter design can be solved by decreasing the number of operators. Usingthese techniques shows the efficiency by reducing area when compared to previously used algorithms designed.

Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

2020 ◽  
Vol 29 (14) ◽  
pp. 2050233
Author(s):  
Zhixi Yang ◽  
Xianbin Li ◽  
Jun Yang
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Electrical Performance ◽  
Approximate Computing ◽  
Dsp Applications

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

An Ultra-Low Power Holter and Low Complexity Design Using Mixed Signal Processor

2013 ◽  
Vol 284-287 ◽  
pp. 1627-1632
Author(s):  
Hsieh Chang Huang ◽  
Ching Tang Hsieh ◽  
Guang Lin Hsieh
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Ecg Signal ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sd Card ◽  
Signal Processor

An ultra-low power, portable, and easily implemented Holter recorder is necessary for patients or researchers of electrocardiogram (ECG). Such a Holter recorder with off-the-shelf components is realized with mixed signal processor (MSP) in this paper. To decrease the complexity of analog circuits and the interference of 60 Hz noise from power line, we use the MSP to implement a finite impulse response (FIR) filter which is equiripple design. We also integrate the ring buffer for the input samples and the symmetrical characteristic of the FIR filter for efficiently computing convolution. The experimental results show that the ECG output signal with the PQRST feature is easy to be distinguished. This ECG signal is recorded for 24 hours using a SD card. Furthermore, the ECG signal is transmitted with a smartphone via Bluetooth to decrease the burden of the Holter recorder. As a result, this paper uses the Lomb method for the spectral analysis of Heart Rate Variability (HRV) better than Fast Fourier Transform (FFT).

scholarly journals FIR Filter Design using Finfets at 22nm Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1292-1295
Keyword(s):  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Fir Filters ◽  
Short Channel ◽  
Channel Effects ◽  
Complex Circuits ◽  
Fir Filter Design

Finite Impulse Response (FIR) filters are the most significantdevice in digital signal processing.In many Digital Signal Processing applications like wireless communication, image and video processing FIR filters are used.Digital FIR filters primarily consists of multipliers, adders and delay elements. Area, power optimization and speed are the key design metrics of FiniteImpulse Response filter.As more electronic devices are battery operated, power consumption constraint becomes a major issue. Multipliers are the core of FIR filters. They consume a lot of energy and are generally complex circuits. With each new process technologies, the short channel effects limit the performance of FIR filters at nano regime. Various architectures have been proposed to enhance the performance of FIR filter. In this paper, FIR filter is designed using FINFETs at 22nm technology using Hspice software.

scholarly journals Proposing a new variable window for better side lobe reduction

2019 ◽  
Vol 8 (9) ◽  
pp. 1107-1112
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Power Loss ◽  
Finite Impulse Response ◽  
Variable Parameter ◽  
Digital Signal ◽  
Side Lobe ◽  
Fir Filter ◽  
Side Lobe Level ◽  
Kaiser Window

Digital signal processing is most widely used to process the signal. In digital signal processing filters are used to remove some unwanted constituents from aspired signal. Windowing is a scheme of finite impulse response filters. Present paper proposes a new versatile window function. It has two variable parameters first one is window span N and another changeable parameter is r. when the value of variable parameter r increases width of major lobe of window also increases with better side lobe reduction and vice versa. Gaussian window and Kaiser window are the well-known variable windows. This paper shows that the proposed window has more desirable results in comparison of Gaussian and Kaiser window with low power loss and better side lobe reduction. To achieve minimum power loss peak side lobe level should have to minimum. Proposed window has low peak side lobe level (-17.681dB) in comparison of Gaussian (-11.836dB) and Kaiser window (-6.9704dB). Proposed work shows that the proposed window has finer spectral characteristic then Gaussian and Kaiser window. FIR filter formed by applying proposed window has narrow -3dB bandwidth (2π×0.320 rad/sample) corresponding to FIR filter formed by using Gaussian and Kaiser window. Ripple ratio of FIR filter plotted by applying proposed window (-144.321dB) is less corresponding to FIR filter delineated by using Gaussian and Kaiser which indicates that the proposed window will give better side lobe rejection and reduce the aliasing problem. In the biomedical field noise present in ECG signal can also reduce by using proposed window.

A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design

2019 ◽  
Vol 29 (01) ◽  
pp. 2050014
Author(s):  
C. Ranjith ◽  
S. P. Joy Vasantha Rani
Keyword(s):  
Hardware Implementation ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Adaptive Genetic Algorithm ◽  
Ip Core ◽  
Complete Evaluation ◽  
Flexible System ◽  
On Chip ◽  
The Impact

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

Efficient FIR Filter Architecture using FPGA

2020 ◽  
Vol 13 (1) ◽  
pp. 91-98
Author(s):  
Ahmed K. Jameil ◽  
Yassir A. Ahmed ◽  
Saad Albawi
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Fir Filters ◽  
Filter Architecture ◽  
Circuit Techniques ◽  
And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

ECG Noise Removal Using Modified Distributed Arithmetic Based Finite Impulse Response Filter

2021 ◽  
Vol 11 (5) ◽  
pp. 1444-1452
Author(s):  
A. Uma ◽  
P. Kalpana
Keyword(s):  
Finite Impulse Response ◽  
Signal To Noise Ratio ◽  
Human Life ◽  
Stress Test ◽  
Noise Removal ◽  
Fir Filter ◽  
Signal Acquisition ◽  
Distributed Arithmetic ◽  
Hardware Resource ◽  
Baseline Wander

ECG monitoring is essential to support human life. During signal acquisition, the signals are contaminated by various noises that occur due to different sources. This paper focuses on Baseline wander and Muscle Artifact noise removal using Distributed Arithmetic (DA) based FIR filters. An area-efficient modified DA based FIR filter consists of LUT-less structure and used for noise removal. The performance of the modified DA based FIR filter is compared with the conventional DA FIR filter. An arbitrary real-time ECG record is taken from MIT-BIH database and Baseline Wander noise, Muscle artifact noises are taken from MIT-BIH noise stress test database. The performance of both filters is evaluated in terms of output Signal to Noise Ratio (SNR) and Mean Square Error (MSE). For Baseline wander noise removal, the modified DA based FIR filter produces high output SNR and also low MSE of 76.6% than the conventional filter. Similarly, for Muscle Artifact noise removal, it produces high SNR, and MSE is reduced to 73.8%. A modified DA based FIR filter is synthesized for the target FPGA device Spartan3E XC3s2000-4fg900 and hardware resource utilization is presented.

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