A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design

2019 ◽  
Vol 29 (01) ◽  
pp. 2050014
Author(s):  
C. Ranjith ◽  
S. P. Joy Vasantha Rani
Keyword(s):  
Hardware Implementation ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Adaptive Genetic Algorithm ◽  
Ip Core ◽  
Complete Evaluation ◽  
Flexible System ◽  
On Chip ◽  
The Impact

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Energy Efficiency ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Building Blocks ◽  
Fir Filter ◽  
Content Type ◽  
Filter Length

Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

scholarly journals FIR Filter Design using Finfets at 22nm Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1292-1295
Keyword(s):  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Fir Filters ◽  
Short Channel ◽  
Channel Effects ◽  
Complex Circuits ◽  
Fir Filter Design

Finite Impulse Response (FIR) filters are the most significantdevice in digital signal processing.In many Digital Signal Processing applications like wireless communication, image and video processing FIR filters are used.Digital FIR filters primarily consists of multipliers, adders and delay elements. Area, power optimization and speed are the key design metrics of FiniteImpulse Response filter.As more electronic devices are battery operated, power consumption constraint becomes a major issue. Multipliers are the core of FIR filters. They consume a lot of energy and are generally complex circuits. With each new process technologies, the short channel effects limit the performance of FIR filters at nano regime. Various architectures have been proposed to enhance the performance of FIR filter. In this paper, FIR filter is designed using FINFETs at 22nm technology using Hspice software.

scholarly journals Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and KoggeStone Adder

2019 ◽  
Vol 8 (2) ◽  
pp. 6138-6141
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Propagation Delay ◽  
Fir Filter ◽  
Filter Synthesis ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Effective Performance

32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.

Implementation of the Finite Impulse Response (FIR) Filter on the DSK TMS320C6713 Transceiver Using Windowing Techniques

2018 ◽  
Vol 6 (1) ◽  
pp. 1-8
Author(s):  
Adella Acqha Vico Addina
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Bandpass Filters ◽  
Fir Filter ◽  
Test Results ◽  
Rectangular Window ◽  
Filter Performance ◽  
Highpass Filter ◽  
Low Pass ◽  
High Pass

In this study, implementing the FIR filter with the Blackman window and Rectangular window methods with the types of low pass, highpass, and bandpass filters using 2 DSK TMS320C6713 boards as sender (Tx) and receiver (Rx) using the code composer studio (CCS) V software program. .3.1, which will then be displayed on Matlab to observe the output results. From the test results, data will be obtained which are then analyzed to determine the filter performance of the design results and the real implementation results using the DSK TMS320C6713. The results showed that the design of the low pass, high pass and bandpass filters was in accordance with the desired specifications, although in the highpass filter design, the filter results were still incomplete.

scholarly journals Design of a Low-Order FIR Filter for a High-Frequency Square-Wave Voltage Injection Method of the PMLSM Used in Maglev Train

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 729 ◽  
Author(s):  
He Zhao ◽  
Liwei Zhang ◽  
Jie Liu ◽  
Chao Zhang ◽  
Jiao Cai ◽  
...  
Keyword(s):  
High Frequency ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Design Method ◽  
Fir Filter ◽  
Maglev Train ◽  
High Frequency Signal ◽  
Injection Method ◽  
High Frequency Response ◽  
Low Order

In position sensorless control based on a high-frequency pulsating voltage injection method, filters are used to complete the extraction of high-frequency response signals for position observation. A finite impulse response (FIR) filter has the advantages of good stability and linear phase. However, the FIR filter designed by using traditional methods has a high order which will cause a large time delay. This paper proposes a low-order FIR filter design method for a high-frequency signal injection method in the permanent magnet linear synchronous motor. Based on the frequency characteristics of the current signal, the requirement that the FIR filter needs to meet were analyzed. According to the amplitude–frequency characteristic of the FIR filter, these requirements were converted into constraint equations. By solving these equations, the coefficient of the FIR filter could be obtained. The simulation and experiment results showed the effectiveness of this low-order FIR filter.

scholarly journals Investigation of Intermittent Resistive Faults in Digital CMOS Circuits

2015 ◽  
Vol 25 (03) ◽  
pp. 1640023 ◽  
Author(s):  
Hans G. Kerkhoff ◽  
Hassan Ebrahimi
Keyword(s):  
Hardware Implementation ◽  
Occurrence Rate ◽  
Cmos Circuits ◽  
Cmos Circuit ◽  
Data Logging ◽  
Digital Cmos ◽  
Short Pulses ◽  
Scientific Challenge ◽  
On Chip ◽  
The Impact

No fault found (NFF) is a major threat in extremely dependable high-end process node integrated systems, in e.g., avionics. One category of NFFs is the intermittent resistive fault (IRF), often originating from bad (e.g., via- or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g., one month, while the duration of the defect can be as short as 50[Formula: see text]ns, thus to evoke and detect these faults is a huge scientific challenge. Two methods to detect short pulses induced by IRFs are proposed. To improve the task of maintenance of avionics and reduce the current high debugging costs, an on-chip data logging system with time stamp and stored environmental conditions is introduced. Finally, a hardware implementation of an IRF generator is presented.

scholarly journals Design of Finite Impulse Response Filters Based on Genetic Algorithm

2013 ◽  
Vol 6 (3) ◽  
pp. 28-39
Author(s):  
Raaed Faleh Hassan ◽  
Ali Subhi Abbood
Keyword(s):  
Genetic Algorithm ◽  
Impulse Response ◽  
Optimization Problems ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Optimal Solution ◽  
Fir Filter ◽  
Language Version ◽  
Finite Impulse Response Filters ◽  
Matlab Programming

Genetic Algorithms (GAs) are used to solve many optimization problems in science and engineering such as pattern recognition, robotics, biology, medicine, and many other applications. The aim of this paper is to describe a method of designing Finite Impulse Response (FIR) filter using Genetic Algorithm (GA). In this paper, the Genetic Algorithm not only used for searching the optimal coefficients, but also it is used to find the minimum number of Taps, and hence minimize the number of multipliers and adders that can be used in the design of the FIR filter. The Evolutionary Programming is the best search procedure and most powerful than Linear Programming in providing the optimal solution that is desired to minimize the ripple content in both passband and stopband. The algorithm generates a population of genomes that represents the filter coefficient and the number of taps, where new genomes are generated by crossover and mutation operations methods. Our proposed genetic technique has able to give better result compare to other method.The FIR filter design using Genetic Algorithm is simulated using MATLAB programming language version 7.6.0.324 (R2008a).

scholarly journals VLSI Implementation of Digital Filter using Novel RTSD Adder and Booth Multiplier

2020 ◽  
Vol 9 (3) ◽  
pp. 4131-4139
Keyword(s):  
Impulse Response ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Fir Filters ◽  
Binary Digit ◽  
Booth Multiplier ◽  
Speed Optimization ◽  
Fir Filter Design ◽  
Convolution Equations

Finite Impulse Response (FIR) filters are most important element in signal processing and communication. Area and speed optimization are the essential necessities of FIR filter design. This work looks at the design of Finite Impulse Response (FIR) filters from an arithmetic perspective. Since the fundamental arithmetic operations in the convolution equations are addition and multiplication, they are the objectives of the design analysis. For multiplication, Booth encoding is utilized in order to lessen the quantity of partial products. Consequently, considering carry-propagation free addition strategies should improve the addition operation of the filter. The redundant ternary signed-digit (RTSD) number framework is utilized to speedup addition in the filter. The redundant ternary representation utilizes more bits than required to denote the single binary digit because of which most numbers have several representations. This special behavior of RTSD allows the addition along with the absence of typical carry propagation. Xilinx ISE design suite 14.5 is used for the design and validation of proposed method. From the implementation result, the proposed design of FIR filter is compared with other conventional techniques to show the better performance by means of power, area and delay.

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