ECG Noise Removal Using Modified Distributed Arithmetic Based Finite Impulse Response Filter

2021 ◽  
Vol 11 (5) ◽  
pp. 1444-1452
Author(s):  
A. Uma ◽  
P. Kalpana
Keyword(s):  
Finite Impulse Response ◽  
Signal To Noise Ratio ◽  
Human Life ◽  
Stress Test ◽  
Noise Removal ◽  
Fir Filter ◽  
Signal Acquisition ◽  
Distributed Arithmetic ◽  
Hardware Resource ◽  
Baseline Wander

ECG monitoring is essential to support human life. During signal acquisition, the signals are contaminated by various noises that occur due to different sources. This paper focuses on Baseline wander and Muscle Artifact noise removal using Distributed Arithmetic (DA) based FIR filters. An area-efficient modified DA based FIR filter consists of LUT-less structure and used for noise removal. The performance of the modified DA based FIR filter is compared with the conventional DA FIR filter. An arbitrary real-time ECG record is taken from MIT-BIH database and Baseline Wander noise, Muscle artifact noises are taken from MIT-BIH noise stress test database. The performance of both filters is evaluated in terms of output Signal to Noise Ratio (SNR) and Mean Square Error (MSE). For Baseline wander noise removal, the modified DA based FIR filter produces high output SNR and also low MSE of 76.6% than the conventional filter. Similarly, for Muscle Artifact noise removal, it produces high SNR, and MSE is reduced to 73.8%. A modified DA based FIR filter is synthesized for the target FPGA device Spartan3E XC3s2000-4fg900 and hardware resource utilization is presented.

VLSI Design and Comparison of DA and LMS Based Reconfigurable FIR Filter

2016 ◽  
Vol 5 (2) ◽  
pp. 124
Author(s):  
P. Hemanthkumar ◽  
Y. Sai Kiran ◽  
V. Nava Teja
Keyword(s):  
Performance Metrics ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Consumption Energy ◽  
The Look ◽  
Suitable Area

<p>Here, we exhibit the design optimization of one- and two-dimensional fully-pipelined computing structures for area-delay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. This plan is found to offer a flexible choice of the address length of the look-up-tables (LUT) for DA-based computation to determine suitable area-time trade-off. It is seen that by using smaller address-lengths for DA-based computing units, it is possible to decrease the memory-size but on the other side that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density and energy throughput are estimated for different filter orders and address-lengths. Obtained results on analysis shows that performance metrics of the proposed implementation is broadly in line with theoretical expectations. We have seen that the choice of address-length M=4 gives the best of area-delay power-efficient realizations of the FIR filter for different filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.</p>

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

scholarly journals Design of parallel and pipelined DA based OBC fir filter for software defined radio

2019 ◽  
Vol 14 (3) ◽  
pp. 1228
Author(s):  
Rajmohan Madasamy ◽  
Himanshu Shekhar
Keyword(s):  
Software Defined Radio ◽  
Finite Impulse Response ◽  
New Technology ◽  
Intermediate Frequency ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Binary Coding ◽  
Processing Block ◽  
Address Line

Software Defined Radio (SDR) is a new technology used to implement different wireless communication standard for mobile communication. The Intermediate Frequency (IF) block is the most demanding block in software defined radio. The most important task in intermediate processing block is digital filtering which is carried out by Finite Impulse Response (FIR) filter. One of the major techniques for the calculation of inner product is Distributed Arithmetic (DA) based FIR filter which uses Look Up Table (LUT) to eliminate the need of multiplier. The efficiency of the DA filter is affected with the increasing number of address line and also due to its serial operation. To overcome this problem parallel and pipeline based DA filter using Offset Binary Coding (OBC) for Two Bit At A Time (2-BAAT) is proposed. Our proposed method achieves less area, low power consumption and nominal delay for SDR application.

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic

2016 ◽  
Vol 25 (07) ◽  
pp. 1650073 ◽  
Author(s):  
Subodh Kumar Singhal ◽  
Basant Kumar Mohanty
Keyword(s):  
Variable Coefficient ◽  
Complexity Analysis ◽  
Finite Impulse Response ◽  
Clock Cycle ◽  
Theoretical Estimate ◽  
Parallel Architecture ◽  
Block Size ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Filter Length

In this paper, we performed the complexity analysis of fixed-coefficient and variable-coefficient distributed arithmetic (DA)-based finite impulse response (FIR) filter structures to observe the effect of LUT decomposition on the area complexity of DA structure. The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism. An appropriate selection of LUT decomposition factor, and introducing higher level of parallelism in the computation could improve the area-delay efficiency of both fixed-coefficient and variable-coefficient DA-based FIR structures. Based on these findings, we have proposed bit-parallel block-based DA structures, for fixed-coefficient and variable-coefficient FIR. The proposed structures process one block of input samples and produce one block of outputs in every clock cycle. Theoretical estimate shows that the proposed fixed-coefficient structure, for block-size 8 and filter-length 32, involves eight times more ROM-LUT words, eight times more adders, two less registers, and offers eight times higher throughput-rate than the existing similar structure. For the same block-size and filter-length, the proposed variable-coefficient structure involves 7.2 times more adders, the same number of registers, eight times more MUXes, and offers eight times higher throughput than the best available similar structure. Synthesis result shows that the proposed fixed-coefficient structure for block-size 8 and filter-length 32 involve 47% less area delay product (ADP) and 42% less energy per sample (EPS) than the existing structure and offers nearly eight times higher throughput than others. For the same block-size and filter-length, the proposed structure for variable-coefficient FIR involves 71% less ADP and 65% less EPS than the similar existing structures.

scholarly journals A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1937
Author(s):  
Ying Zhang ◽  
Yubin Zhu ◽  
Kaining Han ◽  
Junchao Wang ◽  
Jianhao Hu
Keyword(s):  
Hardware Implementation ◽  
Finite Impulse Response ◽  
Signal To Noise Ratio ◽  
Digital Signal ◽  
Low Complexity ◽  
Fir Filter ◽  
Stream Length ◽  
Stochastic Computing ◽  
Dsp Systems ◽  
Bit Stream

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

Dispersive noise removal in t-x space: Application to Arctic data

Geophysics ◽  
1988 ◽  
Vol 53 (3) ◽  
pp. 346-358 ◽  
Author(s):  
Greg Beresford‐Smith ◽  
Rolf N. Rango
Keyword(s):  
Signal To Noise Ratio ◽  
Noise Analysis ◽  
Noise Removal ◽  
North Slope ◽  
Frequency Bandwidth ◽  
The North ◽  
North Slope Of Alaska ◽  
Seismic Records ◽  
Time Offset ◽  
Undersampled Data

Strongly dispersive noise from surface waves can be attenuated on seismic records by Flexfil, a new prestack process which uses wavelet spreading rather than velocity as the criterion for noise discrimination. The process comprises three steps: trace‐by‐trace compression to collapse the noise to a narrow fan in time‐offset (t-x) space; muting of the noise in this narrow fan; and inverse compression to recompress the reflection signals. The process will work on spatially undersampled data. The compression is accomplished by a frequency‐domain, linear operator which is independent of trace offset. This operator is the basis of a robust method of dispersion estimation. A flexural ice wave occurs on data recorded on floating ice in the near offshore of the North Slope of Alaska. It is both highly dispersed and of broad frequency bandwidth. Application of Flexfil to these data can increase the signal‐to‐noise ratio up to 20 dB. A noise analysis obtained from a microspread record is ideal to use for dispersion estimation. Production seismic records can also be used for dispersion estimation, with less accurate results. The method applied to field data examples from Alaska demonstrates significant improvement in data quality, especially in the shallow section.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

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